Sat, 10 Dec 2011 14:12:09 +0100
implemented responsewire in CU firmware
blackbox/interrupts.c | file | annotate | diff | comparison | revisions | |
blackbox/lowlevel.c | file | annotate | diff | comparison | revisions | |
blackbox/lowlevel.h | file | annotate | diff | comparison | revisions | |
blackbox/main.c | file | annotate | diff | comparison | revisions | |
blackbox/main.h | file | annotate | diff | comparison | revisions | |
pitlane/main.c | file | annotate | diff | comparison | revisions | |
trackswitch/main.c | file | annotate | diff | comparison | revisions |
--- a/blackbox/interrupts.c Sat Dec 10 10:51:24 2011 +0100 +++ b/blackbox/interrupts.c Sat Dec 10 14:12:09 2011 +0100 @@ -1,5 +1,5 @@ ISR ( TIMER1_COMPA_vect ) { - //PORTC ^= _BV(PC0); // DEBUG OUTPUT SYSTEM CLOCK + PORTC ^= _BV(PC0); // DEBUG OUTPUT SYSTEM CLOCK // trigger packet transfer: if (sysclk_packettimer == 14) { // 15*500 = 7500 NS @@ -16,6 +16,7 @@ } ISR ( TIMER2_COMP_vect ) { + uint8_t i; //OCR2 = TIMER2_50US; // make sure that timer2 is 50µs !!! // data packet timer 100µs pro bit... if (transmit_len >= 0xFE) { @@ -35,6 +36,35 @@ response_len = 0; TIMSK |= _BV(TOIE0); + // Try to read the stuff on the response wire + TIMSK &= ~_BV(OCIE2); // temporarily disable timer2 interrupts + responsewire_data = 0; + // wait a little and look if wire goes low + i = 100; + while ( ((PIN(RESPONSEWIRE_PORT) & _BV(RESPONSEWIRE_PIN)) != 0) && (i>0) ) { + i--; + _delay_us(5); + } + if (i>0) { + // response incoming! + // start feew µs later + _delay_us(5); + for (i=16; i>0; i--) { // start receiving all 16 bits + PORTC ^= _BV(PC1); // DEBUG + responsewire_data = (responsewire_data << 1); // shift bits + if ((PIN(RESPONSEWIRE_PORT) & _BV(RESPONSEWIRE_PIN)) == 0) // phsyical low == logic 1 + responsewire_data |= 1; + _delay_us(48); // get to next bit + } + itoa(responsewire_data, s, 16); + RS232_puts("RW:"); + RS232_puts(s); + RS232_putc('\n'); + } + TIMSK |= _BV(OCIE2); //enable timer2 interrupt + // end reading response wire + + } } else { uint16_t bit = (1<<(transmit_len & 0b01111111));
--- a/blackbox/lowlevel.c Sat Dec 10 10:51:24 2011 +0100 +++ b/blackbox/lowlevel.c Sat Dec 10 14:12:09 2011 +0100 @@ -111,7 +111,7 @@ // setup data bit + carid timer TCCR2 = (1<<CS21) | (1<<WGM21); //divide by 8, set compare match OCR2 = TIMER2_50US; - TIMSK |= 1<<OCIE2; //enable timer2 interrupt + TIMSK |= _BV(OCIE2); //enable timer2 interrupt // enable carid interrupts MCUCR = _BV(ISC00) | _BV(ISC01) | _BV(ISC10) | _BV(ISC11); // INT0/1 rising edge @@ -123,7 +123,7 @@ TCCR1B = (1<<CS11) | (1<<WGM12); //divide by 8, set compare match (1mhz clock) OCR1A = TIMER1_500NS; //OCR1A = TIMER1_7500NS; - TIMSK |= 1<<OCIE1A; //enable timer1 interrupt + TIMSK |= _BV(OCIE1A); //enable timer1 interrupt RS232_puts_p(PSTR("FreeSlot Blackbox v")); RS232_puts(VERSION); @@ -133,7 +133,7 @@ -void check_rails_shortcut(void) { +uint8_t check_rails_shortcut(void) { // check for short circuit on the rails uint8_t i = 100; if ((PIN(RAIL_DETECT_PORT) & _BV(RAIL_DETECT)) == 0) { @@ -167,4 +167,5 @@ } } } + return 0; } \ No newline at end of file
--- a/blackbox/lowlevel.h Sat Dec 10 10:51:24 2011 +0100 +++ b/blackbox/lowlevel.h Sat Dec 10 14:12:09 2011 +0100 @@ -5,7 +5,7 @@ void LED(uint8_t num, uint8_t state); void LEDS_OFF(void); void init_hardware(void); -void check_rails_shortcut(void); +uint8_t check_rails_shortcut(void); #endif
--- a/blackbox/main.c Sat Dec 10 10:51:24 2011 +0100 +++ b/blackbox/main.c Sat Dec 10 14:12:09 2011 +0100 @@ -74,6 +74,7 @@ volatile uint8_t transmit_len_next; volatile uint8_t transmit_len_queue; +volatile uint16_t responsewire_data = 0; volatile uint16_t response; volatile uint8_t response_len; volatile uint8_t timer0_delay;
--- a/blackbox/main.h Sat Dec 10 10:51:24 2011 +0100 +++ b/blackbox/main.h Sat Dec 10 14:12:09 2011 +0100 @@ -4,7 +4,7 @@ #include <avr/wdt.h> #include <stdint.h> -#define VERSION "1.3" +#define VERSION "1.4" #define COUNTDOWN_DELAY 10 // x/10 seconds @@ -16,6 +16,9 @@ #define MODUL_ST4 PD5 #define MODUL_ST6 PD6 +#define RESPONSEWIRE_PORT MODUL_PORT +#define RESPONSEWIRE_PIN MODUL_ST4 + #define I2C_PORT PORTC #define I2C_SCL PC0 #define I2C_SDA PC1
--- a/pitlane/main.c Sat Dec 10 10:51:24 2011 +0100 +++ b/pitlane/main.c Sat Dec 10 14:12:09 2011 +0100 @@ -94,7 +94,6 @@ uint8_t enable = DDR(RESPONSE_PORT) | _BV(RESPONSE_PIN); uint8_t disable = DDR(RESPONSE_PORT) & ~_BV(RESPONSE_PIN); data |= 0b100000000000001; // make sure start/stop bits are set - data = 0b1010101010101011; while (index != 0) { if ((data & 1) != 0) { DDR(RESPONSE_PORT) = enable; // enable response output @@ -348,9 +347,9 @@ // set inside status for (tmp=0; tmp<MAX_SLOTS; tmp++) if (slot[tmp].inside) { - response = (1 | ((tmp)<<1) | (4 << 4)); slot[tmp].inside = 0; } + response = (1 | (0b111 <<1) | (4 << 4)); RS232_puts_p(PSTR("PIT:EXIT\n")); }
--- a/trackswitch/main.c Sat Dec 10 10:51:24 2011 +0100 +++ b/trackswitch/main.c Sat Dec 10 14:12:09 2011 +0100 @@ -17,12 +17,14 @@ #define PULSE_PORT PORTD #define PULSE_BIT PD2 -#define RESPONSE_PORT PORTD -#define RESPONSE_PIN PD5 + +#define RESPONSE_PORT PORTC +#define RESPONSE_PIN PC1 + #define SOLENOID_A_PORT PORTB #define SOLENOID_B_PORT PORTB -#define TRACKSWITCH_TYPE 2 // 1=double, 2=single +#define TRACKSWITCH_TYPE 1 // 1=double, 2=single #define SOLENOID_A_PIN PB1 #define SOLENOID_B_PIN PB2 @@ -67,7 +69,6 @@ uint8_t enable = DDR(RESPONSE_PORT) | _BV(RESPONSE_PIN); uint8_t disable = DDR(RESPONSE_PORT) & ~_BV(RESPONSE_PIN); data |= 0b100000000000001; // make sure start/stop bits are set - data = 0b1010101010101011; while (index != 0) { if ((data & 1) != 0) { DDR(RESPONSE_PORT) = enable; // enable response output @@ -248,7 +249,7 @@ //OSCCAL = 0xa0; // internal oscillator @ 4 mhz.... doesnt work accurate! RS232_init(); // initialize RS232 interface - RS232_puts_p(PSTR("Freeslot TrackSwitch v1.2\n")); + RS232_puts_p(PSTR("Freeslot TrackSwitch v1.3\n")); sei();