comparison: trackswitch/main.c
trackswitch/main.c
- changeset 69
- 27c0c0095e26
- parent 62
- 66dd5763dfb3
- child 70
- 3a57b7a70683
equal
deleted
inserted
replaced
| 68:c3460121ad8b | 69:27c0c0095e26 |
|---|---|
| 15 ISR ( USART_RXC_vect ) { | 15 ISR ( USART_RXC_vect ) { |
| 16 } | 16 } |
| 17 | 17 |
| 18 #define PULSE_PORT PORTD | 18 #define PULSE_PORT PORTD |
| 19 #define PULSE_BIT PD2 | 19 #define PULSE_BIT PD2 |
| 20 #define RESPONSE_PORT PORTD | 20 |
| 21 #define RESPONSE_PIN PD5 | 21 #define RESPONSE_PORT PORTC |
| 22 #define RESPONSE_PIN PC1 | |
| 23 | |
| 22 #define SOLENOID_A_PORT PORTB | 24 #define SOLENOID_A_PORT PORTB |
| 23 #define SOLENOID_B_PORT PORTB | 25 #define SOLENOID_B_PORT PORTB |
| 24 | 26 |
| 25 #define TRACKSWITCH_TYPE 2 // 1=double, 2=single | 27 #define TRACKSWITCH_TYPE 1 // 1=double, 2=single |
| 26 | 28 |
| 27 #define SOLENOID_A_PIN PB1 | 29 #define SOLENOID_A_PIN PB1 |
| 28 #define SOLENOID_B_PIN PB2 | 30 #define SOLENOID_B_PIN PB2 |
| 29 | 31 |
| 30 // internal analog comparator doesnt work well | 32 // internal analog comparator doesnt work well |
| 65 */ | 67 */ |
| 66 uint8_t index = 16; // bit count maximum | 68 uint8_t index = 16; // bit count maximum |
| 67 uint8_t enable = DDR(RESPONSE_PORT) | _BV(RESPONSE_PIN); | 69 uint8_t enable = DDR(RESPONSE_PORT) | _BV(RESPONSE_PIN); |
| 68 uint8_t disable = DDR(RESPONSE_PORT) & ~_BV(RESPONSE_PIN); | 70 uint8_t disable = DDR(RESPONSE_PORT) & ~_BV(RESPONSE_PIN); |
| 69 data |= 0b100000000000001; // make sure start/stop bits are set | 71 data |= 0b100000000000001; // make sure start/stop bits are set |
| 70 data = 0b1010101010101011; | |
| 71 while (index != 0) { | 72 while (index != 0) { |
| 72 if ((data & 1) != 0) { | 73 if ((data & 1) != 0) { |
| 73 DDR(RESPONSE_PORT) = enable; // enable response output | 74 DDR(RESPONSE_PORT) = enable; // enable response output |
| 74 } else { | 75 } else { |
| 75 DDR(RESPONSE_PORT) = disable; // disable response output | 76 DDR(RESPONSE_PORT) = disable; // disable response output |
| 246 //OSCCAL = 0xa0; | 247 //OSCCAL = 0xa0; |
| 247 //OSCCAL = 0x9A; | 248 //OSCCAL = 0x9A; |
| 248 //OSCCAL = 0xa0; // internal oscillator @ 4 mhz.... doesnt work accurate! | 249 //OSCCAL = 0xa0; // internal oscillator @ 4 mhz.... doesnt work accurate! |
| 249 | 250 |
| 250 RS232_init(); // initialize RS232 interface | 251 RS232_init(); // initialize RS232 interface |
| 251 RS232_puts_p(PSTR("Freeslot TrackSwitch v1.2\n")); | 252 RS232_puts_p(PSTR("Freeslot TrackSwitch v1.3\n")); |
| 252 sei(); | 253 sei(); |
| 253 | 254 |
| 254 | 255 |
| 255 DDR(SOLENOID_A_PORT) |= _BV(SOLENOID_A_PIN); | 256 DDR(SOLENOID_A_PORT) |= _BV(SOLENOID_A_PIN); |
| 256 DDR(SOLENOID_B_PORT) |= _BV(SOLENOID_B_PIN); | 257 DDR(SOLENOID_B_PORT) |= _BV(SOLENOID_B_PIN); |
