Mercurial > hg-public > freeslot / file diff

--- a/blackbox/interrupts.c	Sat Dec 10 10:51:24 2011 +0100
+++ b/blackbox/interrupts.c	Sat Dec 10 14:12:09 2011 +0100
@@ -1,5 +1,5 @@
 ISR ( TIMER1_COMPA_vect ) {
-    //PORTC ^= _BV(PC0); // DEBUG OUTPUT SYSTEM CLOCK
+    PORTC ^= _BV(PC0); // DEBUG OUTPUT SYSTEM CLOCK
 
     // trigger packet transfer:
     if (sysclk_packettimer == 14) { // 15*500 = 7500 NS
@@ -16,6 +16,7 @@
 }
 
 ISR ( TIMER2_COMP_vect ) {
+    uint8_t i;
     //OCR2 = TIMER2_50US; // make sure that timer2 is 50µs !!!
     // data packet timer 100µs pro bit...
     if (transmit_len >= 0xFE) {
@@ -35,6 +36,35 @@
             response_len = 0;
             TIMSK |= _BV(TOIE0);
 
+            // Try to read the stuff on the response wire
+            TIMSK &= ~_BV(OCIE2); // temporarily disable timer2 interrupts
+            responsewire_data = 0;
+            // wait a little and look if wire goes low
+            i = 100;
+            while ( ((PIN(RESPONSEWIRE_PORT) & _BV(RESPONSEWIRE_PIN)) != 0) && (i>0) ) {
+                i--;
+                _delay_us(5);
+            }
+            if (i>0) {
+                // response incoming!
+                // start feew µs later
+                _delay_us(5);
+                for (i=16; i>0; i--) { // start receiving all 16 bits
+    PORTC ^= _BV(PC1); // DEBUG
+                    responsewire_data = (responsewire_data << 1); // shift bits
+                    if ((PIN(RESPONSEWIRE_PORT) & _BV(RESPONSEWIRE_PIN)) == 0) // phsyical low == logic 1
+                        responsewire_data |= 1;
+                    _delay_us(48); // get to next bit
+                }
+                itoa(responsewire_data, s, 16);
+                RS232_puts("RW:");
+                RS232_puts(s);
+                RS232_putc('\n');
+            }
+            TIMSK |= _BV(OCIE2); //enable timer2 interrupt
+            // end reading response wire
+
+
         }
     } else {
         uint16_t bit = (1<<(transmit_len & 0b01111111));