65 volatile uint8_t data_len = 0; |
65 volatile uint8_t data_len = 0; |
66 volatile uint8_t bitbuf_len = 0; |
66 volatile uint8_t bitbuf_len = 0; |
67 volatile uint16_t bitbuf = 0; |
67 volatile uint16_t bitbuf = 0; |
68 |
68 |
69 volatile uint8_t response = 0; |
69 volatile uint8_t response = 0; |
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70 volatile uint8_t response_car = 0; |
70 uint8_t self_id = 0b1111; // ONLY ONE pitlane |
71 uint8_t self_id = 0b1111; // ONLY ONE pitlane |
71 |
72 |
72 void solenoid_delay(void) { |
73 void solenoid_delay(void) { |
73 _delay_ms(2); |
74 _delay_ms(2); |
74 } |
75 } |
75 |
76 |
76 void send_response(uint16_t data) { |
77 void send_response(uint8_t car, uint8_t status) { |
77 /* frame format: |
78 /* frame format: |
78 1 startbit |
79 1 startbit |
79 2 car id |
80 2 car id bit 1 |
80 3 car id |
81 3 car id bit 2 |
81 4 car id |
82 4 car id bit 3 |
82 5 track change status bit 1 |
83 5 track change status bit 1 |
83 6 track change status bit 2 |
84 6 track change status bit 2 |
84 7 sender id |
85 7 track change status bit 3 |
85 8 sender id |
86 8 track change status bit 4 |
86 9 sender id |
87 9 sender id bit 1 |
87 9 sender id |
88 10 sender id bit 2 |
88 10 device type |
89 11 sender id bit 3 |
89 11 device type |
90 12 sender id bit 4 |
90 12 device type |
91 13 device type bit 1 |
91 13 device type |
92 14 device type bit 2 |
92 14 reserved |
93 15 device type bit 3 |
93 15 reserved |
|
94 16 stopbit |
94 16 stopbit |
95 */ |
95 */ |
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96 uint16_t data; |
|
97 // produce packet |
|
98 data = ((car & 0b111) << 1) | ((status & 0b1111) << 4) | ((self_id & 0b1111) << 8) | (TRACKSWITCH_TYPE << 12); |
|
99 data |= 0b100000000000001; // make sure start/stop bits are set |
|
100 |
96 uint8_t index = 16; // bit count maximum |
101 uint8_t index = 16; // bit count maximum |
97 uint8_t enable = DDR(RESPONSE_PORT) | _BV(RESPONSE_PIN); |
102 uint8_t enable = DDR(RESPONSE_PORT) | _BV(RESPONSE_PIN); |
98 uint8_t disable = DDR(RESPONSE_PORT) & ~_BV(RESPONSE_PIN); |
103 uint8_t disable = DDR(RESPONSE_PORT) & ~_BV(RESPONSE_PIN); |
99 data |= 0b100000000000001; // make sure start/stop bits are set |
|
100 while (index != 0) { |
104 while (index != 0) { |
101 if ((data & 1) != 0) { |
105 if ((data & 1) != 0) { |
102 DDR(RESPONSE_PORT) = enable; // enable response output |
106 DDR(RESPONSE_PORT) = enable; // enable response output |
103 } else { |
107 } else { |
104 DDR(RESPONSE_PORT) = disable; // disable response output |
108 DDR(RESPONSE_PORT) = disable; // disable response output |
146 clock = (bitbuf >> 6) & 0b00000111; |
150 clock = (bitbuf >> 6) & 0b00000111; |
147 slot[clock].speed = (bitbuf >> 1) & 0x0F; |
151 slot[clock].speed = (bitbuf >> 1) & 0x0F; |
148 slot[clock].trackswitch = (bitbuf >> 5) & 1; |
152 slot[clock].trackswitch = (bitbuf >> 5) & 1; |
149 // current response for this car? |
153 // current response for this car? |
150 if (response != 0) { |
154 if (response != 0) { |
151 if ( ((response & 0b00001110) >> 1) == clock) { |
155 if ( response_car == clock) { |
152 // add our ID to response: |
156 // add our ID to response: |
153 send_response(response | (self_id << 6)); |
157 send_response(clock, response); |
154 response = 0; |
158 response = 0; |
155 } |
159 } |
156 } |
160 } |
157 } |
161 } |
158 |
162 |
276 |
280 |
277 while (1) { |
281 while (1) { |
278 // main loop |
282 // main loop |
279 |
283 |
280 /* |
284 /* |
281 0 = AA |
285 1 = AA |
282 1 = AB |
286 2 = AB |
283 2 = BB |
287 3 = BB |
284 3 = BA |
288 4 = BA |
285 4 = ZZ -> pitlane exit |
|
286 5 = BC |
289 5 = BC |
|
290 6 = ZZ -> pitlane exit |
287 */ |
291 */ |
288 if (sens[0].car != sens[0].state) { |
292 if (sens[0].car != sens[0].state) { |
289 sens[0].state = sens[0].car; |
293 sens[0].state = sens[0].car; |
290 #if (TRACKSWITCH_TYPE != TYPE_PITLANE) |
294 #if (TRACKSWITCH_TYPE != TYPE_PITLANE) |
291 if ( (sens[0].state != 0) && (slot[sens[0].state-1].trackswitch == 0) && (slot[sens[0].state-1].speed>0) ) { |
295 if ( (sens[0].state != 0) && (slot[sens[0].state-1].trackswitch == 0) && (slot[sens[0].state-1].speed>0) ) { |
292 response = (1 | ((sens[0].state-1)<<1) | (1 << 4)); |
296 response = 2; |
|
297 response_car = sens[0].state - 1; |
293 |
298 |
294 // set inside status |
299 // set inside status |
295 slot[sens[0].state].inside = 1; |
300 slot[sens[0].state].inside = 1; |
296 |
301 |
297 // trigger solenoid A |
302 // trigger solenoid A |
317 |
323 |
318 |
324 |
319 if (sens[1].car != sens[1].state) { |
325 if (sens[1].car != sens[1].state) { |
320 sens[1].state = sens[1].car; |
326 sens[1].state = sens[1].car; |
321 if ( (sens[1].state != 0) && (slot[sens[1].state-1].trackswitch == 0) && (slot[sens[1].state-1].speed>0) ) { |
327 if ( (sens[1].state != 0) && (slot[sens[1].state-1].trackswitch == 0) && (slot[sens[1].state-1].speed>0) ) { |
322 response = (1 | ((sens[1].state-1)<<1) | (5 << 4)); |
328 response = 5; |
|
329 response_car = sens[1].state - 1; |
323 |
330 |
324 // set inside status |
331 // set inside status |
325 slot[sens[1].state-1].inside = 1; |
332 slot[sens[1].state-1].inside = 1; |
326 |
333 |
327 // trigger solenoid B |
334 // trigger solenoid B |
350 // set inside status |
358 // set inside status |
351 for (tmp=0; tmp<MAX_SLOTS; tmp++) |
359 for (tmp=0; tmp<MAX_SLOTS; tmp++) |
352 if (slot[tmp].inside) { |
360 if (slot[tmp].inside) { |
353 slot[tmp].inside = 0; |
361 slot[tmp].inside = 0; |
354 } |
362 } |
355 response = (1 | (0b111 <<1) | (4 << 4)); |
363 response = 6; |
|
364 response_car = 0; |
356 RS232_puts_p(PSTR("PIT:EXIT\n")); |
365 RS232_puts_p(PSTR("PIT:EXIT\n")); |
357 } |
366 } |
358 |
367 |
359 if (sens[2].car != sens[2].state) { |
368 if (sens[2].car != sens[2].state) { |
360 sens[2].state = sens[2].car; |
369 sens[2].state = sens[2].car; |
361 if (sens[2].state != 0) { |
370 if (sens[2].state != 0) { |
362 response = (1 | ((sens[2].state-1)<<1) | (4 << 4)); |
371 response = 6; |
|
372 response_car = sens[2].state-1; |
363 |
373 |
364 // set inside status |
374 // set inside status |
365 slot[sens[2].state-1].inside = 0; |
375 slot[sens[2].state-1].inside = 0; |
366 |
376 |
367 RS232_putc('Z'); |
377 RS232_putc('Z'); |