40 } break; |
40 } break; |
41 } |
41 } |
42 } |
42 } |
43 |
43 |
44 void init_hardware(void) { |
44 void init_hardware(void) { |
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45 // reset all ports to input, no pullup |
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46 DDRA = 0; PORTA = 0; |
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47 DDRB = 0; PORTB = 0; |
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48 DDRC = 0; PORTC = 0; |
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49 DDRD = 0; PORTD = 0; |
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50 |
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51 |
45 RS232_init(); // initialize RS485 interface |
52 RS232_init(); // initialize RS485 interface |
46 RS232_puts_p(PSTR("CARRERA beta loading\n")); |
53 RS232_puts_p(PSTR("CARRERA beta loading\n")); |
47 |
54 |
48 initADC(); |
55 initADC(); |
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56 SFIOR = 0; |
49 |
57 |
50 // set LED output |
58 // set LED output |
51 DDR(LED1_PORT) |= _BV(LED1); |
59 DDR(LED1_PORT) |= _BV(LED1); |
52 DDR(LED2_PORT) |= _BV(LED2); |
60 DDR(LED2_PORT) |= _BV(LED2); |
53 DDR(LED3_PORT) |= _BV(LED3); |
61 DDR(LED3_PORT) |= _BV(LED3); |
57 // set Controller Input Pull-UPs |
65 // set Controller Input Pull-UPs |
58 CONTROLLER_PORT |= (_BV(CONTROLLER1_SW) | _BV(CONTROLLER2_SW) | _BV(CONTROLLER3_SW) | _BV(CONTROLLER4_SW)); |
66 CONTROLLER_PORT |= (_BV(CONTROLLER1_SW) | _BV(CONTROLLER2_SW) | _BV(CONTROLLER3_SW) | _BV(CONTROLLER4_SW)); |
59 |
67 |
60 // switch pull-ups |
68 // switch pull-ups |
61 SW_FUEL_PORT |= _BV(SW_FUEL); |
69 SW_FUEL_PORT |= _BV(SW_FUEL); |
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70 SW_START_PORT |= _BV(SW_START); |
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71 SW_PACECAR_PORT |= _BV(SW_PACECAR); |
62 |
72 |
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73 // control outputs |
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74 DDR(LAP_COUNTER_PORT) |= _BV(LAP_COUNTER); |
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75 |
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76 // setup rail control |
63 //RAIL_DETECT_PORT |= _BV(RAIL_DETECT); // enable internal pull-up |
77 //RAIL_DETECT_PORT |= _BV(RAIL_DETECT); // enable internal pull-up |
64 DDR(RAIL_POWER_PORT) |= _BV(RAIL_POWER); |
78 DDR(RAIL_POWER_PORT) |= _BV(RAIL_POWER); |
65 |
79 |
66 |
80 // display init sequence on LEDs |
67 LED(1, 1); _delay_ms(50); |
81 LED(1, 1); _delay_ms(50); |
68 LED(2, 1); _delay_ms(50); |
82 LED(2, 1); _delay_ms(50); |
69 LED(3, 1); _delay_ms(50); |
83 LED(3, 1); _delay_ms(50); |
70 LED(4, 1); _delay_ms(50); |
84 LED(4, 1); _delay_ms(50); |
71 LED(5, 1); _delay_ms(50); |
85 LED(5, 1); _delay_ms(50); |
80 TCCR0 = (1<<CS01); //divide by 8 |
94 TCCR0 = (1<<CS01); //divide by 8 |
81 // interrupt enable + tcnt0 set in timer2 |
95 // interrupt enable + tcnt0 set in timer2 |
82 |
96 |
83 |
97 |
84 // setup data bit timer |
98 // setup data bit timer |
85 TCCR2 = (1<<CS21); //divide by 8 |
99 TCCR2 = (1<<CS21) | (1<<WGM21); //divide by 8, set compare match |
86 TCCR2 |= (1<<WGM21); // set compare match |
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87 OCR2 = TIMER2_50US; |
100 OCR2 = TIMER2_50US; |
88 TIMSK |= 1<<OCIE2; //enable timer2 interrupt |
101 TIMSK |= 1<<OCIE2; //enable timer2 interrupt |
89 |
102 |
90 // setup data packet timer |
103 // setup data packet timer |
91 //TCCR1A = (1<<COM1A1); |
104 //TCCR1A = (1<<COM1A1); |
92 TCCR1B = (1<<CS11); //divide by 8 |
105 TCCR1B = (1<<CS11) | (1<<WGM12); //divide by 8, set compare match |
93 TCCR1B |= (1<<WGM12); // set compare match |
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94 //TCCR1B = (1<<CS11) | (1<<CS10); //divide by 64 |
106 //TCCR1B = (1<<CS11) | (1<<CS10); //divide by 64 |
95 //TCNT1 = TIMER_7500NS; |
107 //TCNT1 = TIMER_7500NS; |
96 OCR1A = TIMER1_7500NS; |
108 OCR1A = TIMER1_7500NS; |
97 TIMSK |= 1<<OCIE1A; //enable timer1 interrupt |
109 TIMSK |= 1<<OCIE1A; //enable timer1 interrupt |
98 |
110 |