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1 | #include <avr/interrupt.h> |
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2 | #include <avr/io.h> |
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3 | #include <avr/wdt.h> |
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4 | #include <avr/eeprom.h> |
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5 | #include <stdlib.h> |
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6 | #include <stdint.h> |
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7 | #include <avr/pgmspace.h> |
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8 | #include <util/delay.h> |
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9 | |
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10 | #include "main.h" |
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11 | |
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12 | #include "driver/rs232.h" |
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13 | #include "driver/adc.h" |
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14 | |
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15 | #include "lowlevel.h" |
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16 | |
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17 | //#include "driver/manchester.h" |
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18 | |
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19 | /* |
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20 | // Hardware config |
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21 | #define LAP_COUNTER_PORT PORTB |
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22 | #define LAP_COUNTER PB2 |
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23 | |
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24 | #define MODUL_PORT PORTD |
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25 | #define MODUL_ST4 PD5 |
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26 | #define MODUL_ST6 PD6 |
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27 | |
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28 | #define I2C_PORT PORTC |
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29 | #define I2C_SDA PC0 |
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30 | #define I2C_SCL PC1 |
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31 | |
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32 | |
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33 | #define SW_PACECAR_PORT PORTC |
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34 | #define SW_START_PORT PORTB |
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35 | #define SW_TANK_PORT PORTB |
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36 | #define SW_PACECAR PC6 |
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37 | #define SW_TANK PB0 |
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38 | #define SW_START PB1 |
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39 | |
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40 | #define SPEAKER_PORT PORTD |
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41 | #define SPEAKER PD7 |
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42 | |
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43 | */ |
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44 | |
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45 | |
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46 | void init_hardware(void) { |
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47 | RS232_init(); // initialize RS485 interface |
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48 | RS232_puts_p(PSTR("CARRERA beta loading\n")); |
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49 | |
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50 | initADC(); |
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51 | |
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52 | // set LED output |
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53 | DDR(LED1_PORT) |= _BV(LED1); |
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54 | DDR(LED2_PORT) |= _BV(LED2); |
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55 | DDR(LED3_PORT) |= _BV(LED3); |
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56 | DDR(LED4_PORT) |= _BV(LED4); |
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57 | DDR(LED5_PORT) |= _BV(LED5); |
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58 | |
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59 | // set Controller Input Pull-UPs |
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60 | CONTROLLER_PORT |= (_BV(CONTROLLER1_SW) | _BV(CONTROLLER2_SW) | _BV(CONTROLLER3_SW) | _BV(CONTROLLER4_SW)); |
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61 | |
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62 | // switch pull-ups |
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63 | SW_FUEL_PORT |= _BV(SW_FUEL); |
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64 | |
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65 | //RAIL_DETECT_PORT |= _BV(RAIL_DETECT); // enable internal pull-up |
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66 | DDR(RAIL_POWER_PORT) |= _BV(RAIL_POWER); |
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67 | |
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68 | |
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69 | LED(1, 1); _delay_ms(50); |
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70 | LED(2, 1); _delay_ms(50); |
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71 | LED(3, 1); _delay_ms(50); |
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72 | LED(4, 1); _delay_ms(50); |
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73 | LED(5, 1); _delay_ms(50); |
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74 | LED(1, 0); _delay_ms(50); |
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75 | LED(2, 0); _delay_ms(50); |
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76 | LED(3, 0); _delay_ms(50); |
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77 | LED(4, 0); _delay_ms(50); |
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78 | LED(5, 0); _delay_ms(50); |
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79 | |
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80 | //TCCR0 = (1<<CS01); //divide by 8 |
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81 | |
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82 | |
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83 | // setup data bit timer |
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84 | TCCR2 = (1<<CS21); //divide by 8 |
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85 | TCCR2 |= (1<<WGM21); // set compare match |
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86 | OCR2 = TIMER2_50US; |
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87 | TIMSK |= 1<<OCIE2; //enable timer2 interrupt |
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88 | |
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89 | // setup data packet timer |
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90 | //TCCR1A = (1<<COM1A1); |
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91 | TCCR1B = (1<<CS11); //divide by 8 |
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92 | TCCR1B |= (1<<WGM12); // set compare match |
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93 | //TCCR1B = (1<<CS11) | (1<<CS10); //divide by 64 |
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94 | //TCNT1 = TIMER_7500NS; |
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95 | OCR1A = TIMER1_7500NS; |
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96 | TIMSK |= 1<<OCIE1A; //enable timer1 interrupt |
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97 | |
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98 | RS232_puts_p(PSTR("INIT OK\n")); |
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99 | |
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100 | } |
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101 | |
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102 | |
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103 | |
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104 | volatile uint8_t datalen = 0; |
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105 | char data[10]; // 8 bytes data buffer + string termination |
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106 | |
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107 | static char buffer[RS232_BUFSIZE+1]; |
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108 | static uint8_t buffer_len; |
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109 | |
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110 | |
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111 | // USART0 RX interrupt |
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112 | ISR ( USART_RXC_vect ) { |
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113 | char c = UDR; |
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114 | |
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115 | // check for buffer overflow |
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116 | if (buffer_len==sizeof(buffer)) { |
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117 | buffer_len=0; |
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118 | if (c == 27) { |
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119 | // escape sequence, store to empty buffer |
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120 | buffer[buffer_len++] = c; |
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121 | } |
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122 | } else { |
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123 | // collect characters until end of line |
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124 | if (c == 27) { |
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125 | // escape sequence, clear buffer |
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126 | buffer_len = 0; |
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127 | buffer[buffer_len++] = c; |
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128 | } else if ( (c==0xff) && (buffer_len > 3) ) { |
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129 | buffer[buffer_len]=0; |
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130 | |
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131 | // packet end received, parse the received packet |
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132 | |
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133 | // wait for the next packet |
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134 | buffer_len=0; |
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135 | } else { |
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136 | buffer[buffer_len++]=c; |
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137 | } |
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138 | } |
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139 | } |
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140 | |
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141 | |
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142 | volatile uint16_t transmit_buffer; |
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143 | volatile uint16_t transmit_buffer_queue; |
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144 | volatile uint8_t transmit_len; |
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145 | volatile uint8_t transmit_len_next; |
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146 | volatile uint8_t transmit_len_queue; |
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147 | ISR ( TIMER2_COMP_vect ) { |
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148 | //OCR2 = TIMER2_50US; // make sure that timer2 is 50µs !!! |
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149 | // data packet timer 100µs pro bit... |
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150 | if (transmit_len >= 0xFE) { |
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151 | if (transmit_len != 0xFF) { |
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152 | RAIL_POWER_PORT |= _BV(RAIL_POWER); // end of transmission |
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153 | transmit_len = 0xFF; |
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154 | transmit_buffer = transmit_buffer_queue; |
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155 | transmit_buffer_queue = 0; |
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156 | transmit_len_next = transmit_len_queue; |
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157 | } |
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158 | } else { |
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159 | uint16_t bit = (1<<(transmit_len & 0b01111111)); |
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160 | uint16_t clock; |
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161 | if ((transmit_len & 0b10000000) == 0) clock = 0; else clock = 0xffff; |
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162 | if ( ((transmit_buffer ^ clock) & bit) != 0 ) |
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163 | RAIL_POWER_PORT |= _BV(RAIL_POWER); else |
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164 | RAIL_POWER_PORT &= ~_BV(RAIL_POWER); |
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165 | if ( (transmit_len & 0b10000000) == 0 ) { |
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166 | // block 0 |
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167 | //if (transmit_len == 0) transmit_len = 0xFF; else transmit_len |= 0b10000000; // set clock |
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168 | transmit_len |= 0b10000000; // set clock |
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169 | } else { |
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170 | // block 1, output the current bit |
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171 | transmit_len &= 0b01111111; // reset clock |
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172 | //if (transmit_len != 0) transmit_len--; // next bit |
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173 | if (transmit_len == 0) transmit_len = 0xFE; else transmit_len--; // next bit |
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174 | } |
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175 | } |
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176 | } |
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177 | |
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178 | int insert_queue(uint16_t tmp, uint8_t len) { |
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179 | if (transmit_buffer_queue == 0) { |
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180 | transmit_buffer_queue = tmp; |
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181 | transmit_len_queue = len; |
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182 | return 1; |
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183 | } |
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184 | return 0; |
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185 | } |
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186 | |
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187 | |
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188 | int do_controller(uint8_t controller) { |
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189 | // read controller X speed & encode controller data packet |
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190 | uint16_t tmp; |
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191 | switch (controller) { |
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192 | case 0: tmp = getADC(CONTROLLER1_SPEED) / CONTROLLER_DIVISOR; break; |
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193 | case 1: tmp = getADC(CONTROLLER2_SPEED) / CONTROLLER_DIVISOR; break; |
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194 | case 2: tmp = getADC(CONTROLLER3_SPEED) / CONTROLLER_DIVISOR; break; |
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195 | case 3: tmp = getADC(CONTROLLER4_SPEED) / CONTROLLER_DIVISOR; break; |
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196 | case 4: tmp = 0; break; // todo regler 5 |
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197 | case 5: tmp = 0; break; // todo regler 6 |
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198 | } |
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199 | tmp = 0b1000000000 | (controller << 6) | ((tmp & 0xF) << 1); |
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200 | if ( (PIN(SW_FUEL_PORT) & _BV(SW_FUEL)) != 0) tmp |= 1; // benzinstand aktiv - tankmodusschalter |
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201 | if ( (PIN(CONTROLLER_PORT) & _BV(CONTROLLER1_SW)) != 0) { |
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202 | tmp |= (1<<5); |
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203 | LED(controller+1, 0); |
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204 | } else LED(controller+1, 1); |
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205 | |
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206 | return insert_queue(tmp, 9); |
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207 | } |
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208 | |
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209 | unsigned char mirror( unsigned char n ) { |
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210 | // mirror all 8 bits |
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211 | n = ((n >> 1) & 0x55) | ((n << 1) & 0xaa); |
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212 | n = ((n >> 2) & 0x33) | ((n << 2) & 0xcc); |
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213 | n = ((n >> 4) & 0x0f) | ((n << 4) & 0xf0); |
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214 | return n; |
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215 | } |
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216 | |
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217 | |
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218 | int do_program(uint8_t controller, uint8_t command, uint8_t parameter) { |
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219 | // send program data packet |
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220 | uint16_t tmp; |
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221 | tmp = 0b1000000000000 | (mirror(parameter) << 4) | mirror(command)| (mirror(controller) >> 5); |
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222 | |
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223 | return insert_queue(tmp, 12); |
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224 | } |
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225 | |
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226 | int do_active(void) { |
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227 | // send controller active data packet |
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228 | uint16_t tmp = 0b10000000; |
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229 | if ((getADC(CONTROLLER1_SPEED) / CONTROLLER_DIVISOR) > 0) tmp |= 0b11000001; |
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230 | if ((getADC(CONTROLLER2_SPEED) / CONTROLLER_DIVISOR) > 0) tmp |= 0b10100001; |
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231 | if ((getADC(CONTROLLER3_SPEED) / CONTROLLER_DIVISOR) > 0) tmp |= 0b10010001; |
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232 | if ((getADC(CONTROLLER4_SPEED) / CONTROLLER_DIVISOR) > 0) tmp |= 0b10001001; |
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233 | // todo: regler 5 und 6 |
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234 | |
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235 | return insert_queue(tmp, 7); |
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236 | } |
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237 | |
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238 | int do_pace_ghost(void) { |
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239 | // send ghost and pacecar data packet |
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240 | // todo: at the moment, both disabled! |
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241 | uint16_t tmp = 0b1111100000; |
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242 | if ( (PIN(SW_FUEL_PORT) & _BV(SW_FUEL)) != 0) tmp |= 1; // benzinstand aktiv - tankmodusschalter |
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243 | // todo: PC, NH, TK, (KFR, FR) |
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244 | |
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245 | return insert_queue(tmp, 9); |
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246 | } |
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247 | |
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248 | /* |
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249 | TODO: DIE TIMER1 ISR DARF DIE ADC NICHT ABFRAGEN, NICHTMAL PAKETE BAUEN, NUR TRIGGERN |
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250 | DIE PAKETE MÃœSSEN IN DER MAIN UNIT GEBAUT WERDEN UND IN EINE QUEUE GESCHOBEN WERDEN |
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251 | EINES VORBAUEN IN Q+1, DIE TIMER2 ISR MUSS DANN Q = Q+1 und Q+1 = 0 SETZEN, ERST DANN DARF |
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252 | NEUES PAKET IN Q+1 EINGEFÃœGT WERDEN |
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253 | */ |
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254 | |
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255 | |
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256 | ISR ( TIMER1_COMPA_vect ) { |
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257 | //OCR2 = 0xFF; // make sure that timer2 is synced to timer1, give enough cycles to prepare |
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258 | LED(4,2); |
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259 | // trigger packet transfer: |
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260 | transmit_len = transmit_len_next; |
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261 | |
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262 | // here is some more time to do something else... |
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263 | } |
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264 | |
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265 | |
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266 | int main(void) |
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267 | { |
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268 | |
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269 | unsigned char s[30]; |
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270 | uint16_t tmp; |
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271 | uint8_t packet_index = 1; |
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272 | |
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273 | |
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274 | init_hardware(); |
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275 | |
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276 | itoa(TIMER2_50US, s, 10); |
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277 | RS232_puts(s); |
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278 | |
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279 | // switch on rails power |
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280 | RAIL_POWER_PORT |= _BV(RAIL_POWER); |
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281 | |
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282 | while (1) { |
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283 | //RS232_putc(PIN(RAIL_DETECT_PORT)); |
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284 | |
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285 | // check for short circuit on the rails |
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286 | if ((PIN(RAIL_DETECT_PORT) & _BV(RAIL_DETECT)) == 0) { |
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287 | _delay_ms(1); |
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288 | if ((PIN(RAIL_DETECT_PORT) & _BV(RAIL_DETECT)) == 0) { |
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289 | cli(); // disable ALL Interrupts |
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290 | RAIL_POWER_PORT &= ~_BV(RAIL_POWER); // disable rails power |
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291 | RS232_puts_p(PSTR("!!! SHORT CIRCUIT ON RAILS, POWERED OFF !!!\n")); |
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292 | while (1) { |
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293 | LED(1, 0); |
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294 | _delay_ms(100); |
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295 | LED(1, 1); |
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296 | _delay_ms(100); |
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297 | } |
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298 | } |
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299 | } |
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300 | |
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301 | |
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302 | |
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303 | |
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304 | switch (packet_index) { |
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305 | case 1: |
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306 | if (do_program(7, 19, 0)) packet_index++; // reset |
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307 | //do_program(7, 16, 3); // led an startampel |
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308 | //do_program(0, 4, 0); // |
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309 | break; |
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310 | case 2: |
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311 | if (do_pace_ghost()) packet_index++; |
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312 | break; |
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313 | case 3: |
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314 | if (do_active()) packet_index++; |
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315 | break; |
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316 | case 4: |
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317 | if (do_controller(0)) packet_index++; |
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318 | break; |
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319 | case 5: |
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320 | if (do_controller(4)) packet_index++; |
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321 | break; |
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322 | case 6: |
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323 | if (do_controller(1)) packet_index++; |
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324 | break; |
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325 | case 7: |
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326 | if (do_controller(5)) packet_index++; |
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327 | break; |
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328 | case 8: |
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329 | if (do_controller(2)) packet_index++; |
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330 | break; |
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331 | case 9: |
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332 | if (do_active()) packet_index++; |
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333 | break; |
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334 | case 10: |
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335 | if (do_controller(3)) packet_index = 1; |
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336 | // last packet, so reset packet index |
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337 | break; |
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338 | } |
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339 | |
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340 | |
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341 | |
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342 | |
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343 | /* |
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344 | do_controller(0); |
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345 | itoa (transmit_len_queue, s, 10); |
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346 | RS232_puts(s); |
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347 | RS232_putc(' '); |
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348 | itoa (transmit_buffer_queue, s, 2); |
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349 | RS232_puts(s); |
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350 | |
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351 | RS232_putc('\n'); |
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352 | */ |
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353 | /* |
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354 | itoa (tmp, s, 2); |
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355 | RS232_puts(s); |
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356 | RS232_putc('\n'); |
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357 | */ |
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358 | |
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359 | |
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360 | } // main loop end |
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361 | }; |
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362 |