Fri, 09 Dec 2011 19:53:20 +0100
added car5+6 to trackswitch detector
53
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1 | ISR ( TIMER1_COMPA_vect ) { |
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2 | //PORTC ^= _BV(PC0); // DEBUG OUTPUT SYSTEM CLOCK |
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3 | |
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4 | // trigger packet transfer: |
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5 | if (sysclk_packettimer == 14) { // 15*500 = 7500 NS |
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6 | transmit_len = transmit_len_next; |
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7 | sysclk_packettimer = 0; |
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8 | } else sysclk_packettimer++; |
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9 | // here is some more time to do something else... |
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10 | |
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11 | // reset both car counters to overflow |
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12 | car0_old = TIMER1_500NS; |
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13 | car1_old = TIMER1_500NS; |
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14 | |
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15 | sysclk.value++; // increment 500ns timer |
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16 | } |
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17 | |
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18 | ISR ( TIMER2_COMP_vect ) { |
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19 | //OCR2 = TIMER2_50US; // make sure that timer2 is 50µs !!! |
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20 | // data packet timer 100µs pro bit... |
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21 | if (transmit_len >= 0xFE) { |
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22 | if (transmit_len != 0xFF) { |
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23 | RAIL_POWER_PORT |= _BV(RAIL_POWER); // end of transmission |
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24 | transmit_len = 0xFF; |
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25 | transmit_buffer = transmit_buffer_queue; |
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26 | transmit_buffer_queue = 0; |
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27 | transmit_len_next = transmit_len_queue; |
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28 | |
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29 | // start the response receiver timer |
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30 | // TODO: only on 8 timeslots, not on every transmission |
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31 | // TODO: give slot number to timer - then store the transmission to 8 slots array |
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32 | TCNT0 = TIMER0_250US; |
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33 | timer0_delay = TIMER0_2300NS; |
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34 | response = 0; |
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35 | response_len = 0; |
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36 | TIMSK |= _BV(TOIE0); |
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37 | |
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38 | } |
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39 | } else { |
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40 | uint16_t bit = (1<<(transmit_len & 0b01111111)); |
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41 | uint16_t clock; |
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42 | if ((transmit_len & 0b10000000) == 0) clock = 0; else clock = 0xffff; |
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43 | if ( ((transmit_buffer ^ clock) & bit) != 0 ) |
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44 | RAIL_POWER_PORT |= _BV(RAIL_POWER); else |
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45 | RAIL_POWER_PORT &= ~_BV(RAIL_POWER); |
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46 | if ( (transmit_len & 0b10000000) == 0 ) { |
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47 | // block 0 |
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48 | //if (transmit_len == 0) transmit_len = 0xFF; else transmit_len |= 0b10000000; // set clock |
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49 | transmit_len |= 0b10000000; // set clock |
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50 | } else { |
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51 | // block 1, output the current bit |
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52 | transmit_len &= 0b01111111; // reset clock |
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53 | //if (transmit_len != 0) transmit_len--; // next bit |
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54 | if (transmit_len == 0) transmit_len = 0xFE; else transmit_len--; // next bit |
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55 | } |
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56 | } |
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57 | } |
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58 | |
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59 | |
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60 | ISR ( TIMER0_OVF_vect ) { |
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61 | // TODO: last bit should be set by the sender, not from us! |
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62 | TCNT0 = TIMER0_250US; |
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63 | if (timer0_delay == 0) { |
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64 | RAIL_POWER_PORT &= ~_BV(RAIL_POWER); // pull rails low |
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65 | _delay_us(28); // wait some cycles |
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66 | if ((PIN(RAIL_DETECT_PORT) & _BV(RAIL_DETECT)) != 0) { // check for logic zero |
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67 | if (response == 0) { |
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68 | // there is no start bit, so stop the timer and cancel response receiving |
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69 | TIMSK &= ~_BV(TOIE0); |
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70 | } else { |
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71 | // we received a bit (logic low) |
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72 | response = response << 1; |
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73 | response_len++; |
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74 | } |
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75 | } else { |
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76 | // okay, we have logic high |
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77 | response = response << 1; |
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78 | response |= 1; |
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79 | response_len++; |
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80 | } |
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81 | if (response_len == 15) { // maximum response length reached |
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82 | RAIL_POWER_PORT |= _BV(RAIL_POWER); // restore rails power |
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83 | TIMSK &= ~_BV(TOIE0); |
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84 | } else { |
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85 | _delay_us(20); // wait some cycles |
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86 | RAIL_POWER_PORT |= _BV(RAIL_POWER); // restore rails power |
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87 | } |
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88 | } else timer0_delay--; // 2.3 ms delay not reached yet |
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89 | } |
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90 | |
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91 | ISR (INT0_vect) { |
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92 | // car0 detector |
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93 | uint16_t tmp = 0; |
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94 | car0_new = TCNT1; // get current counter |
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95 | if (car0_old < car0_new) { |
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96 | // calculate difference |
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97 | if (car0 == 0) tmp = car0_new-car0_old; |
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98 | if ( (tmp > 54) && (tmp < 74) ) car0 = 1; |
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99 | if ( (tmp > 118) && (tmp < 138) ) car0 = 2; |
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100 | if ( (tmp > 186) && (tmp < 206) ) car0 = 3; |
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101 | if ( (tmp > 246) && (tmp < 266) ) car0 = 4; |
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102 | if ( (tmp > 310) && (tmp < 330) ) car0 = 5; |
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103 | if ( (tmp > 374) && (tmp < 394) ) car0 = 6; |
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104 | } |
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105 | car0_old = car0_new; |
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106 | } |
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107 | |
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108 | ISR (INT1_vect) { |
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109 | // car1 detector |
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110 | uint16_t tmp = 0; |
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111 | car1_new = TCNT1; // get current counter |
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112 | if (car1_old < car1_new) { |
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113 | // calculate difference |
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114 | if (car1 == 0) tmp = car1_new-car1_old; |
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115 | if ( (tmp > 54) && (tmp < 74) ) car1 = 1; |
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116 | if ( (tmp > 118) && (tmp < 138) ) car1 = 2; |
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117 | if ( (tmp > 186) && (tmp < 206) ) car1 = 3; |
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118 | if ( (tmp > 246) && (tmp < 266) ) car1 = 4; |
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119 | if ( (tmp > 310) && (tmp < 330) ) car1 = 5; |
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120 | if ( (tmp > 374) && (tmp < 394) ) car1 = 6; |
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121 | } |
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122 | car1_old = car1_new; |
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123 | } |
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124 | |
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125 | |
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126 | ISR (INT2_vect) { |
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127 | // Lap counter Interrupt |
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128 | // do not know if this ever occurs ?! this is normally an output pin to trigger the counter start |
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129 | } |