# HG changeset patch
# User mdd
# Date 1491242655 -7200
# Node ID d26669bf424e38f4f0147d74b47c19e66cbea2d1
# Parent  a01a3fd320739ba869c5b2a1c304bd75d7c40262
binary stl precompile

diff -r a01a3fd32073 -r d26669bf424e data.py
--- a/data.py	Mon Apr 03 19:40:06 2017 +0200
+++ b/data.py	Mon Apr 03 20:04:15 2017 +0200
@@ -8,6 +8,9 @@
 	"12S"	: [204, 550, 12, 15.4],
 	"12L"	: [171, 690, 12, 14.5],
 	"15"	: [204, 640, 15, 18.1],
+	"16"	: [204, 670, 16, 19.5],
+	"18"	: [204, 710, 18, 20.5],
+	"20"	: [204, 810, 20, 22.0],
 }
 
 # Standard Rohrdurchmesser (Mr. Baumarkt)
diff -r a01a3fd32073 -r d26669bf424e stl.py
--- a/stl.py	Mon Apr 03 19:40:06 2017 +0200
+++ b/stl.py	Mon Apr 03 20:04:15 2017 +0200
@@ -1,4 +1,5 @@
 import data, os, config, subprocess
+import vtk
 
 OPENSCAD_MODULES = """
 module tank(x, r, h) {
@@ -38,6 +39,15 @@
         output,
         config.TMP_SCAD
         ])
+    # convert to binary
+    reader = vtk.vtkSTLReader()
+    reader.SetFileName(output)
+    reader.Update()
+    write = vtk.vtkSTLWriter()
+    write.SetFileTypeToBinary()
+    write.SetInput(reader.GetOutput())
+    write.SetFileName(output)
+    write.Write() 
 
 def precompile_all_stl():
     base = os.path.abspath('stl')