diff -r a01a3fd32073 -r d26669bf424e stl.py
--- a/stl.py	Mon Apr 03 19:40:06 2017 +0200
+++ b/stl.py	Mon Apr 03 20:04:15 2017 +0200
@@ -1,4 +1,5 @@
 import data, os, config, subprocess
+import vtk
 
 OPENSCAD_MODULES = """
 module tank(x, r, h) {
@@ -38,6 +39,15 @@
         output,
         config.TMP_SCAD
         ])
+    # convert to binary
+    reader = vtk.vtkSTLReader()
+    reader.SetFileName(output)
+    reader.Update()
+    write = vtk.vtkSTLWriter()
+    write.SetFileTypeToBinary()
+    write.SetInput(reader.GetOutput())
+    write.SetFileName(output)
+    write.Write() 
 
 def precompile_all_stl():
     base = os.path.abspath('stl')