# HG changeset patch # User Malte Bayer # Date 1323420015 -3600 # Node ID f659e6faf18fa684437d64b9ece4c1d5905e84be # Parent 6b26d7e3ecd05544294a9d502d953326d96e9605 moved ISRs from main.c to interrupts.c diff -r 6b26d7e3ecd0 -r f659e6faf18f blackbox/interrupts.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/blackbox/interrupts.c Fri Dec 09 09:40:15 2011 +0100 @@ -0,0 +1,125 @@ +ISR ( TIMER1_COMPA_vect ) { + //PORTC ^= _BV(PC0); // DEBUG OUTPUT SYSTEM CLOCK + + // trigger packet transfer: + if (sysclk_packettimer == 14) { // 15*500 = 7500 NS + transmit_len = transmit_len_next; + sysclk_packettimer = 0; + } else sysclk_packettimer++; + // here is some more time to do something else... + + // reset both car counters to overflow + car0_old = TIMER1_500NS; + car1_old = TIMER1_500NS; + + sysclk.value++; // increment 500ns timer +} + +ISR ( TIMER2_COMP_vect ) { + //OCR2 = TIMER2_50US; // make sure that timer2 is 50µs !!! + // data packet timer 100µs pro bit... + if (transmit_len >= 0xFE) { + if (transmit_len != 0xFF) { + RAIL_POWER_PORT |= _BV(RAIL_POWER); // end of transmission + transmit_len = 0xFF; + transmit_buffer = transmit_buffer_queue; + transmit_buffer_queue = 0; + transmit_len_next = transmit_len_queue; + + // start the response receiver timer + // TODO: only on 8 timeslots, not on every transmission + // TODO: give slot number to timer - then store the transmission to 8 slots array + TCNT0 = TIMER0_250US; + timer0_delay = TIMER0_2300NS; + response = 0; + response_len = 0; + TIMSK |= _BV(TOIE0); + + } + } else { + uint16_t bit = (1<<(transmit_len & 0b01111111)); + uint16_t clock; + if ((transmit_len & 0b10000000) == 0) clock = 0; else clock = 0xffff; + if ( ((transmit_buffer ^ clock) & bit) != 0 ) + RAIL_POWER_PORT |= _BV(RAIL_POWER); else + RAIL_POWER_PORT &= ~_BV(RAIL_POWER); + if ( (transmit_len & 0b10000000) == 0 ) { + // block 0 + //if (transmit_len == 0) transmit_len = 0xFF; else transmit_len |= 0b10000000; // set clock + transmit_len |= 0b10000000; // set clock + } else { + // block 1, output the current bit + transmit_len &= 0b01111111; // reset clock + //if (transmit_len != 0) transmit_len--; // next bit + if (transmit_len == 0) transmit_len = 0xFE; else transmit_len--; // next bit + } + } +} + + +ISR ( TIMER0_OVF_vect ) { +// TODO: last bit should be set by the sender, not from us! + TCNT0 = TIMER0_250US; + if (timer0_delay == 0) { + RAIL_POWER_PORT &= ~_BV(RAIL_POWER); // pull rails low + _delay_us(28); // wait some cycles + if ((PIN(RAIL_DETECT_PORT) & _BV(RAIL_DETECT)) != 0) { // check for logic zero + if (response == 0) { + // there is no start bit, so stop the timer and cancel response receiving + TIMSK &= ~_BV(TOIE0); + } else { + // we received a bit (logic low) + response = response << 1; + response_len++; + } + } else { + // okay, we have logic high + response = response << 1; + response |= 1; + response_len++; + } + if (response_len == 15) { // maximum response length reached + RAIL_POWER_PORT |= _BV(RAIL_POWER); // restore rails power + TIMSK &= ~_BV(TOIE0); + } else { + _delay_us(20); // wait some cycles + RAIL_POWER_PORT |= _BV(RAIL_POWER); // restore rails power + } + } else timer0_delay--; // 2.3 ms delay not reached yet +} + +ISR (INT0_vect) { + // car0 detector + uint16_t tmp = 0; + car0_new = TCNT1; // get current counter + if (car0_old < car0_new) { + // calculate difference + if (car0 == 0) tmp = car0_new-car0_old; + if ( (tmp > 54) && (tmp < 74) ) car0 = 1; + if ( (tmp > 118) && (tmp < 138) ) car0 = 2; + if ( (tmp > 186) && (tmp < 206) ) car0 = 3; + if ( (tmp > 246) && (tmp < 266) ) car0 = 4; + } + car0_old = car0_new; +} + +ISR (INT1_vect) { + // car1 detector + uint16_t tmp = 0; + car1_new = TCNT1; // get current counter + if (car1_old < car1_new) { + // calculate difference + if (car1 == 0) tmp = car1_new-car1_old; + if ( (tmp > 54) && (tmp < 74) ) car1 = 1; + if ( (tmp > 118) && (tmp < 138) ) car1 = 2; + if ( (tmp > 186) && (tmp < 206) ) car1 = 3; + if ( (tmp > 246) && (tmp < 266) ) car1 = 4; + } + car1_old = car1_new; +} + + +ISR (INT2_vect) { + // Lap counter Interrupt + // do not know if this ever occurs ?! this is normally an output pin to trigger the counter start +} diff -r 6b26d7e3ecd0 -r f659e6faf18f blackbox/main.c --- a/blackbox/main.c Thu Dec 08 17:46:21 2011 +0100 +++ b/blackbox/main.c Fri Dec 09 09:40:15 2011 +0100 @@ -177,7 +177,6 @@ } - int do_controller(uint8_t controller) { // read controller X speed & encode controller data packet uint16_t tmp = 0; @@ -292,131 +291,7 @@ return insert_queue(tmp, 9); } -ISR ( TIMER1_COMPA_vect ) { - //PORTC ^= _BV(PC0); // DEBUG OUTPUT SYSTEM CLOCK - - // trigger packet transfer: - if (sysclk_packettimer == 14) { // 15*500 = 7500 NS - transmit_len = transmit_len_next; - sysclk_packettimer = 0; - } else sysclk_packettimer++; - // here is some more time to do something else... - - // reset both car counters to overflow - car0_old = TIMER1_500NS; - car1_old = TIMER1_500NS; - - sysclk.value++; // increment 500ns timer -} - -ISR ( TIMER2_COMP_vect ) { - //OCR2 = TIMER2_50US; // make sure that timer2 is 50µs !!! - // data packet timer 100µs pro bit... - if (transmit_len >= 0xFE) { - if (transmit_len != 0xFF) { - RAIL_POWER_PORT |= _BV(RAIL_POWER); // end of transmission - transmit_len = 0xFF; - transmit_buffer = transmit_buffer_queue; - transmit_buffer_queue = 0; - transmit_len_next = transmit_len_queue; - - // start the response receiver timer - // TODO: only on 8 timeslots, not on every transmission - // TODO: give slot number to timer - then store the transmission to 8 slots array - TCNT0 = TIMER0_250US; - timer0_delay = TIMER0_2300NS; - response = 0; - response_len = 0; - TIMSK |= _BV(TOIE0); - - } - } else { - uint16_t bit = (1<<(transmit_len & 0b01111111)); - uint16_t clock; - if ((transmit_len & 0b10000000) == 0) clock = 0; else clock = 0xffff; - if ( ((transmit_buffer ^ clock) & bit) != 0 ) - RAIL_POWER_PORT |= _BV(RAIL_POWER); else - RAIL_POWER_PORT &= ~_BV(RAIL_POWER); - if ( (transmit_len & 0b10000000) == 0 ) { - // block 0 - //if (transmit_len == 0) transmit_len = 0xFF; else transmit_len |= 0b10000000; // set clock - transmit_len |= 0b10000000; // set clock - } else { - // block 1, output the current bit - transmit_len &= 0b01111111; // reset clock - //if (transmit_len != 0) transmit_len--; // next bit - if (transmit_len == 0) transmit_len = 0xFE; else transmit_len--; // next bit - } - } -} - - -ISR ( TIMER0_OVF_vect ) { -// TODO: last bit should be set by the sender, not from us! - TCNT0 = TIMER0_250US; - if (timer0_delay == 0) { - RAIL_POWER_PORT &= ~_BV(RAIL_POWER); // pull rails low - _delay_us(28); // wait some cycles - if ((PIN(RAIL_DETECT_PORT) & _BV(RAIL_DETECT)) != 0) { // check for logic zero - if (response == 0) { - // there is no start bit, so stop the timer and cancel response receiving - TIMSK &= ~_BV(TOIE0); - } else { - // we received a bit (logic low) - response = response << 1; - response_len++; - } - } else { - // okay, we have logic high - response = response << 1; - response |= 1; - response_len++; - } - if (response_len == 15) { // maximum response length reached - RAIL_POWER_PORT |= _BV(RAIL_POWER); // restore rails power - TIMSK &= ~_BV(TOIE0); - } else { - _delay_us(20); // wait some cycles - RAIL_POWER_PORT |= _BV(RAIL_POWER); // restore rails power - } - } else timer0_delay--; // 2.3 ms delay not reached yet -} - -ISR (INT0_vect) { - // car0 detector - uint16_t tmp = 0; - car0_new = TCNT1; // get current counter - if (car0_old < car0_new) { - // calculate difference - if (car0 == 0) tmp = car0_new-car0_old; - if ( (tmp > 54) && (tmp < 74) ) car0 = 1; - if ( (tmp > 118) && (tmp < 138) ) car0 = 2; - if ( (tmp > 186) && (tmp < 206) ) car0 = 3; - if ( (tmp > 246) && (tmp < 266) ) car0 = 4; - } - car0_old = car0_new; -} - -ISR (INT1_vect) { - // car1 detector - uint16_t tmp = 0; - car1_new = TCNT1; // get current counter - if (car1_old < car1_new) { - // calculate difference - if (car1 == 0) tmp = car1_new-car1_old; - if ( (tmp > 54) && (tmp < 74) ) car1 = 1; - if ( (tmp > 118) && (tmp < 138) ) car1 = 2; - if ( (tmp > 186) && (tmp < 206) ) car1 = 3; - if ( (tmp > 246) && (tmp < 266) ) car1 = 4; - } - car1_old = car1_new; -} - - -ISR (INT2_vect) { - // Lap counter Interrupt - // do not know if this ever occurs ?! this is normally an output pin to trigger the counter start -} +#include "interrupts.c" void reset_vars(void) { uint8_t i;