# HG changeset patch # User Malte Bayer # Date 1322575568 -3600 # Node ID e333cf0e4d84b6a49bc861a2387c8ac6b41e70cf # Parent 40a309c9c13592ade2bf30ee3652413fe2d90147 finished trackswitch v1.0 - works as original firmware now diff -r 40a309c9c135 -r e333cf0e4d84 trackswitch/main.c --- a/trackswitch/main.c Tue Nov 29 13:42:29 2011 +0100 +++ b/trackswitch/main.c Tue Nov 29 15:06:08 2011 +0100 @@ -17,11 +17,21 @@ #define PULSE_PORT PORTD #define PULSE_BIT PD2 +#define SOLENOID_A_PORT PORTB +#define SOLENOID_A_PIN PB1 +#define SOLENOID_B_PORT PORTB +#define SOLENOID_B_PIN PB2 + volatile uint16_t data = 0; volatile uint8_t data_len = 0; volatile uint8_t bitbuf_len = 0; volatile uint16_t bitbuf = 0; +volatile uint8_t car_speed[8]; +volatile uint8_t car_switch[8]; +volatile uint16_t car0, car1; +volatile uint16_t car0_new, car0_old; +volatile uint16_t car1_new, car1_old; ISR ( INT0_vect ) { GICR &= ~_BV(INT0) ; // Disable INT0 @@ -34,9 +44,7 @@ TIMSK |= _BV(OCIE2); //enable timer2 interrupt } - ISR ( TIMER2_COMP_vect ) { - uint8_t clock; uint8_t state; uint8_t state2; @@ -52,7 +60,16 @@ data_len = (bitbuf_len & 0b00111111); TIMSK &= ~_BV(OCIE2); //disable timer2 interrupt GICR |= _BV(INT0) ; // Enable INT0 - data = bitbuf; // output data + + //data = bitbuf; // output data + // write data of controllers to array + if (data_len == 10) { // controller data packet + clock = (bitbuf >> 6) & 0b00000111; + car_speed[clock] = (bitbuf >> 1) & 0x0F; + car_switch[clock] = (bitbuf >> 5) & 1; + } + + } else { bitbuf_len++; // increment bit counter bitbuf = bitbuf << 1; // shift bits @@ -67,13 +84,9 @@ bitbuf_len &= ~_BV(6); // store new state } } - } -uint16_t car0_new, car0_old; -uint16_t car1_new, car1_old; -volatile uint16_t car0, car1; ISR (TIMER1_OVF_vect) { // reset both car counters to overflow car0_old = 0xffff; @@ -110,22 +123,22 @@ car1_old = car1_new; } -#define OSC_OFFSET 0 + +void solenoid_delay(void) { + _delay_ms(10); +} + int main(void) { - uint16_t i, data_tmp; - uint8_t tmp, datalen_tmp; - unsigned char s[30]; + uint8_t car0_state, car1_state; + car0_state = 1; + car1_state = 1; - - uint8_t car_speed[8]; - uint8_t car_switch[8]; - uint8_t car_switch_old[8]; // setup data bit timer2 TCCR2 = (1<= 5) { - if (datalen_tmp == 13) { // sync to first packet - i = 1; - } else i++; - if (datalen_tmp == 10) { // controller data packet - tmp = (data_tmp >> 6) & 0b111; - if (tmp < 6) { - car_speed[tmp] = (data_tmp >> 1) & 0x0F; - car_switch[tmp] = (data_tmp >> 5) & 1; - } - } + if (car0 != car0_state) { + car0_state = car0; + if ( (car0_state != 0) && (car_switch[car0_state-1] == 0) ) { + // trigger solenoid A + RS232_putc('A'); + RS232_putc('0'+car0_state); + RS232_putc('\n'); + + SOLENOID_A_PORT |= _BV(SOLENOID_A_PIN); + solenoid_delay(); + SOLENOID_A_PORT &= ~_BV(SOLENOID_A_PIN); + solenoid_delay(); } - } - - for (i=0; i<6; i++) { - if (car_switch[i] != car_switch_old[i]) { - RS232_putc('0'+i); - RS232_putc('0'+car_switch[i]); - RS232_putc('\n'); - } - car_switch_old[i] = car_switch[i]; - } + } car0 = 0; -/* - i = get_car(_BV(PD3)); - if (i > 0) { - itoa ( i , s, 10); - RS232_puts(s); - RS232_putc('\n'); - } - _delay_ms(50); -*/ + if (car1 != car1_state) { + car1_state = car1; + if ( (car1_state != 0) && (car_switch[car1_state-1] == 0) ) { + // trigger solenoid A + RS232_putc('B'); + RS232_putc('0'+car1_state); + RS232_putc('\n'); - if (car0 > 0) { - itoa ( car0 , s, 10); - car0 = 0; - RS232_putc('A'); - RS232_puts(s); - RS232_putc('\n'); - } + SOLENOID_B_PORT |= _BV(SOLENOID_B_PIN); + solenoid_delay(); + SOLENOID_B_PORT &= ~_BV(SOLENOID_B_PIN); + solenoid_delay(); + } + } car1 = 0; - if (car1 > 0) { - itoa ( car1 , s, 10); - car1 = 0; - RS232_putc('B'); - RS232_puts(s); - RS232_putc('\n'); - } } // main loop end };