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comparison: carrerashark/main.c

carrerashark/main.c

changeset 38
ff76255904c4
parent 31
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child 39
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equal deleted inserted replaced
37:136a79772098 38:ff76255904c4
10 10
11 #include "driver/rs232.h" 11 #include "driver/rs232.h"
12 #include "util/delay.h" 12 #include "util/delay.h"
13 13
14 14
15 static char buffer[RS232_BUFSIZE+1]; 15 volatile char buffer[RS232_BUFSIZE+1];
16 static uint8_t buffer_len; 16 volatile uint8_t buffer_len = 0;
17 17
18 18 volatile uint8_t showall = 0;
19
20 19
21 // USART0 RX interrupt 20 // USART0 RX interrupt
22 ISR ( USART_RXC_vect ) { 21 ISR ( USART_RXC_vect ) {
23 char c = UDR; 22 char c = UDR;
24 23
33 // collect characters until end of line 32 // collect characters until end of line
34 if (c == 27) { 33 if (c == 27) {
35 // escape sequence, clear buffer 34 // escape sequence, clear buffer
36 buffer_len = 0; 35 buffer_len = 0;
37 buffer[buffer_len++] = c; 36 buffer[buffer_len++] = c;
38 } else if ( (c==0xff) && (buffer_len > 3) ) { 37 } else if ( (c=='\n') && (buffer_len > 3) ) {
39 buffer[buffer_len]=0; 38 buffer[buffer_len]=0;
40 39
41 // packet end received, parse the received packet 40 // packet end received, parse the received packet
41 if (buffer[0] == 'A') {
42 showall = 1;
43 RS232_puts_p(PSTR("Entering Livemode\n"));
44 }
45 if (buffer[0] == 'C') {
46 showall = 0;
47 RS232_puts_p(PSTR("Showing only changes\n"));
48 }
42 49
43 // wait for the next packet 50 // wait for the next packet
44 buffer_len=0; 51 buffer_len=0;
45 } else { 52 } else {
46 buffer[buffer_len++]=c; 53 buffer[buffer_len++]=c;
52 #define PULSE_PORT PORTD 59 #define PULSE_PORT PORTD
53 #define PULSE_BIT PD2 60 #define PULSE_BIT PD2
54 61
55 volatile uint16_t data = 0; 62 volatile uint16_t data = 0;
56 volatile uint8_t data_len = 0; 63 volatile uint8_t data_len = 0;
64 volatile uint16_t response = 0;
65 volatile uint8_t response_len = 0;
57 volatile uint8_t bitbuf_len = 0; 66 volatile uint8_t bitbuf_len = 0;
58 volatile uint16_t bitbuf = 0; 67 volatile uint16_t bitbuf = 0;
59 68
60 volatile uint16_t sysclock = 0; 69 volatile uint8_t sysclock = 0;
61 ISR ( TIMER0_OVF_vect ) { 70 ISR ( TIMER0_OVF_vect ) {
62 PORTD ^= _BV(PD6); 71 PORTD ^= _BV(PD6);
63 if (sysclock != 0xffff) sysclock++; 72 if (sysclock != 0xff) sysclock++;
64 } 73 }
65 74
66 ISR ( INT0_vect ) { 75 ISR ( INT0_vect ) {
67 PORTD ^= _BV(PD3); 76 PORTD ^= _BV(PD3);
68 if (sysclock<10) { 77 if ((sysclock > 0) && (sysclock<10)) {
69 // this is the answer slot start bit?? 78 // this is the answer slot start bit??
70 PORTD ^= _BV(PD7); 79 // configure the bitbuf to start receive of answer data
80 if ((PIN(PULSE_PORT) & _BV(PULSE_BIT)) != 0) {
81 PORTD ^= _BV(PD7); // set indicator
82 OCR2 = TIMER2_250US;
83 GICR &= ~_BV(INT0) ; // Disable INT0
84 bitbuf = 0; // init
85 bitbuf_len = 0b00100000; // init zero, first pulse is checked by timer, set answer receive flag!
86 // START BIT RECEIVED!
87 //OCR2 = TIMER2_250US;
88 TCNT2 = 1;
89 TIMSK |= _BV(OCIE2); //enable timer2 interrupt
90 } else {
91 OCR2 = TIMER2_50US;
92 }
93
71 } else { 94 } else {
72 GICR &= ~_BV(INT0) ; // Disable INT0 95 GICR &= ~_BV(INT0) ; // Disable INT0
73 // Startsignal erkannt, ab hier den Timer2 starten, 96 // Startsignal erkannt, ab hier den Timer2 starten,
74 // der liest dann alle 50µs den Zustand ein und schreibt das 97 // der liest dann alle 50µs den Zustand ein und schreibt das
75 // empfangene Bit in den Puffer 98 // empfangene Bit in den Puffer
76 bitbuf = 0; // init 99 bitbuf = 0; // init
77 bitbuf_len = 0b10000000; // init 1 pulse received 100 bitbuf_len = 0b10000000; // init 1 pulse received
101 OCR2 = TIMER2_50US;
78 TCNT2 = 0; 102 TCNT2 = 0;
79 TIMSK |= _BV(OCIE2); //enable timer2 interrupt 103 TIMSK |= _BV(OCIE2); //enable timer2 interrupt
80 } 104 }
81 } 105 }
82 106
83 107
84 ISR ( TIMER2_COMP_vect ) { 108 ISR ( TIMER2_COMP_vect ) {
85 PORTD ^= _BV(PD4); 109 PORTD ^= _BV(PD4);
86 uint8_t clock; 110 uint8_t clock, state, state2, rxa;
87 uint8_t state; 111
88 uint8_t state2; 112
89 if ((bitbuf_len & 0b10000000) == 0) clock = 0; else clock = 0xff; 113 if ((bitbuf_len & 0b00100000) == 0) rxa = 0; else rxa = 0xff;
90 if ((bitbuf_len & 0b01000000) == 0) state = 0; else state = 0xff;
91 if ((PIN(PULSE_PORT) & _BV(PULSE_BIT)) == 0) state2 = 0; else state2 = 0xff; 114 if ((PIN(PULSE_PORT) & _BV(PULSE_BIT)) == 0) state2 = 0; else state2 = 0xff;
92 115
93 if (clock) { 116 if (rxa == 0) {
94 // second pulse of bit 117 // receive a standard packet
95 bitbuf_len &= ~_BV(7); // switch clock to low 118 if ((bitbuf_len & 0b10000000) == 0) clock = 0; else clock = 0xff;
96 if ((state==state2) & state2) { 119 if ((bitbuf_len & 0b01000000) == 0) state = 0; else state = 0xff;
97 // two cycles high: packet end received 120
98 data_len = (bitbuf_len & 0b00111111); 121 if (clock) {
99 if (data_len == 13) PORTD ^= _BV(6); // debug sync output on program packets 122 // second pulse of bit
123 bitbuf_len &= ~_BV(7); // switch clock to low
124 if ((state==state2) & state2) {
125 // two cycles high: packet end received
126 data_len = (bitbuf_len & 0b00011111);
127 data = bitbuf; // output data
128 if (data_len == 13) PORTD ^= _BV(6); // debug sync output on program packets
129 sysclock = 0; // reset system clock counter
130 TIMSK &= ~_BV(OCIE2); //disable timer2 interrupt
131 GICR |= _BV(INT0); // Enable INT0
132 // GIFR &= ~_BV(INTF0); // clear int0 irq flag
133 } else {
134 bitbuf_len++; // increment bit counter
135 bitbuf = bitbuf << 1; // shift bits
136 if (state2 == 0) bitbuf |= 1; // receive logic one
137 }
138 } else {
139 // first pulse of bit
140 bitbuf_len |= _BV(7); // switch clock to high
141 if (state2) {
142 bitbuf_len |= _BV(6); // store new state
143 } else {
144 bitbuf_len &= ~_BV(6); // store new state
145 }
146 }
147 } else {
148 // receive an answer packet!
149 if ((bitbuf_len & 0xF) < 0xE) {
150 // receive one of max 15 bits to buffer
151 bitbuf_len++;
152 bitbuf = bitbuf << 1; // shift bits
153 if (state2 != 0) bitbuf |= 1; // receive logic one
154 } else {
155 OCR2 = TIMER2_50US;
156 // END OF ANSWER
157 response_len = (bitbuf_len & 0b00011111);
158 response = bitbuf; // output data (full 16bits)
159 PORTD ^= _BV(PD7);
100 TIMSK &= ~_BV(OCIE2); //disable timer2 interrupt 160 TIMSK &= ~_BV(OCIE2); //disable timer2 interrupt
101 GICR |= _BV(INT0); // Enable INT0 161 GICR |= _BV(INT0); // Enable INT0
102 GIFR &= ~_BV(INTF0); // clear int0 irq flag
103 data = bitbuf; // output data
104 sysclock = 0; // reset system clock counter
105 } else {
106 bitbuf_len++; // increment bit counter
107 bitbuf = bitbuf << 1; // shift bits
108 if (state2 == 0) bitbuf |= 1; // receive logic one
109 }
110 } else {
111 // first pulse of bit
112 bitbuf_len |= _BV(7); // switch clock to high
113 if (state2) {
114 bitbuf_len |= _BV(6); // store new state
115 } else {
116 bitbuf_len &= ~_BV(6); // store new state
117 } 162 }
118 } 163 }
119 } 164 }
120 165
121 166
122 167
123 int main(void) 168 int main(void)
124 { 169 {
125 uint8_t i; 170 uint8_t i, cycle_changed;
126 unsigned char s[10]; 171 unsigned char s[10];
127 uint16_t tmp; 172 uint16_t tmp;
128 uint16_t cycle[11]; 173 uint16_t cycle[11];
174 uint16_t cycle_old[11];
129 175
130 // setup data bit timer 176 // setup data bit timer
131 TCCR2 = (1<<CS21) | (1<<WGM21); //divide by 8, set compare match 177 TCCR2 = (1<<CS21) | (1<<WGM21); //divide by 8, set compare match
132 OCR2 = TIMER2_50US; 178 OCR2 = TIMER2_50US;
133 TIMSK |= 1<<OCIE2; //enable timer2 interrupt 179 TIMSK |= 1<<OCIE2; //enable timer2 interrupt
135 // setup system timer 181 // setup system timer
136 TCCR0 = (1<<CS21); //divide by 8 182 TCCR0 = (1<<CS21); //divide by 8
137 TIMSK |= 1<<TOIE0; //enable timer0 interrupt 183 TIMSK |= 1<<TOIE0; //enable timer0 interrupt
138 184
139 185
140 MCUCR = _BV(ISC00); // falling edge 186 MCUCR = _BV(ISC01); // falling edge
141 // MCUCR = _BV(ISC00) | _BV(ISC01); // rising edge 187 // MCUCR = _BV(ISC00) | _BV(ISC01); // rising edge
142 GICR = _BV(INT0) ; // Enable INT0 188 GICR = _BV(INT0) ; // Enable INT0
143 189
144 DDRD |= _BV(PD3) | _BV(PD4) | _BV(PD5) | _BV(PD6) | _BV(PD7); 190 DDRD |= _BV(PD3) | _BV(PD4) | _BV(PD5) | _BV(PD6) | _BV(PD7);
145 PORTD |= _BV(PD7); 191 PORTD |= _BV(PD7);
146 192
147 RS232_init(); // initialize RS232 interface 193 RS232_init(); // initialize RS232 interface
148 RS232_puts_p(PSTR("CarreraShark 1.2\n")); 194 RS232_puts_p(PSTR("CarreraShark 1.2\nA = Show all data live\nC = Show only when data changes"));
149 195
150 sei(); 196 sei();
151 i = 0; 197 i = 0;
152 while (1) { 198 while (1) {
153 // main loop 199 // main loop
200
201 if (response != 0) {
202 RS232_puts_p(PSTR("RX: "));
203 itoa(response, s, 2);
204 response = 0;
205 RS232_puts( s );
206 RS232_putc('\n');
207 while (1) ;
208 }
154 209
155 if (data != 0) { 210 if (data != 0) {
156 if (data_len > 5) { 211 if (data_len > 5) {
157 tmp = data; 212 tmp = data;
158 data = 0; 213 data = 0;
159 if (data_len == 13) { // sync to first packet 214 if (data_len == 13) { // sync to first packet
160 PORTD ^= _BV(PD5); 215 PORTD ^= _BV(PD5);
161 for (i=0; i<10;i++ ) { 216 if (showall == 0) {
162 // output previous cycle data 217 // compare old & new cycle
163 itoa( cycle[i], s, 16); 218 cycle_changed = 0;
164 RS232_putc('0'); 219 for (i=0; i<10;i++ ) if (cycle[i] != cycle_old[i]) cycle_changed = 1;
165 RS232_putc('x');
166 RS232_puts( s );
167 RS232_putc(' ');
168 } 220 }
169 RS232_putc('*'); 221 if ( (showall != 0) || (cycle_changed != 0) ) {
222 for (i=0; i<10;i++ ) {
223 // output previous cycle data
224 itoa( cycle[i], s, 16);
225 RS232_putc('0');
226 RS232_putc('x');
227 RS232_puts( s );
228 RS232_putc(' ');
229 }
230 if (showall != 0) RS232_putc('*'); else RS232_putc('\n');
231 }
232 if (showall == 0) for (i=0; i<10;i++ ) cycle_old[i] = cycle[i];
170 i = 0; 233 i = 0;
171 PORTD ^= _BV(PD5); 234 PORTD ^= _BV(PD5);
172 } 235 }
173 cycle[i] = tmp; 236 cycle[i] = tmp;
174 i++; 237 i++;

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