comparison: blackbox/interrupts.c
blackbox/interrupts.c
- changeset 73
- ec888cfa024e
- parent 69
- 27c0c0095e26
- child 89
- 4b5b4c7ba03d
equal
deleted
inserted
replaced
| 72:60c4b28fd773 | 73:ec888cfa024e |
|---|---|
| 1 ISR ( TIMER1_COMPA_vect ) { | 1 ISR ( TIMER1_COMPA_vect ) { |
| 2 PORTC ^= _BV(PC0); // DEBUG OUTPUT SYSTEM CLOCK | |
| 3 | |
| 4 // trigger packet transfer: | 2 // trigger packet transfer: |
| 5 if (sysclk_packettimer == 14) { // 15*500 = 7500 NS | 3 if (sysclk_packettimer == 14) { // 15*500 = 7500 NS |
| 6 transmit_len = transmit_len_next; | 4 transmit_len = transmit_len_next; |
| 7 sysclk_packettimer = 0; | 5 sysclk_packettimer = 0; |
| 8 } else sysclk_packettimer++; | 6 } else sysclk_packettimer++; |
| 47 } | 45 } |
| 48 if (i>0) { | 46 if (i>0) { |
| 49 // response incoming! | 47 // response incoming! |
| 50 // start feew µs later | 48 // start feew µs later |
| 51 _delay_us(5); | 49 _delay_us(5); |
| 52 for (i=16; i>0; i--) { // start receiving all 16 bits | 50 for (i=16; i>0; i--) { // start receiving all 16 bits -> shift them in same direction as they're shifted out |
| 53 PORTC ^= _BV(PC1); // DEBUG | 51 responsewire_data = (responsewire_data >> 1); // shift bits right, first received = bit0 |
| 54 responsewire_data = (responsewire_data << 1); // shift bits | |
| 55 if ((PIN(RESPONSEWIRE_PORT) & _BV(RESPONSEWIRE_PIN)) == 0) // phsyical low == logic 1 | 52 if ((PIN(RESPONSEWIRE_PORT) & _BV(RESPONSEWIRE_PIN)) == 0) // phsyical low == logic 1 |
| 56 responsewire_data |= 1; | 53 responsewire_data |= 0b1000000000000000; |
| 57 _delay_us(48); // get to next bit | 54 _delay_us(48); // get to next bit |
| 58 } | 55 } |
| 59 itoa(responsewire_data, s, 16); | 56 // we have some little time here to decode the response and do some action for refueling state of cars |
| 60 RS232_puts("RW:"); | 57 decode_responsewire(); |
| 61 RS232_puts(s); | |
| 62 RS232_putc('\n'); | |
| 63 } | 58 } |
| 64 TIMSK |= _BV(OCIE2); //enable timer2 interrupt | 59 TIMSK |= _BV(OCIE2); //enable timer2 interrupt |
| 65 // end reading response wire | 60 // end reading response wire |
| 66 | 61 |
| 67 | 62 |
