Sun, 11 Dec 2011 17:34:40 +0100
finished live CLI, BB firmware improvements and fixes
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1 | #include <avr/interrupt.h> |
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2 | #include <avr/io.h> |
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3 | #include <avr/wdt.h> |
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4 | #include <avr/eeprom.h> |
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5 | #include <stdlib.h> |
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6 | #include <stdint.h> |
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7 | #include <avr/pgmspace.h> |
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8 | |
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9 | #include "main.h" |
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10 | |
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11 | #include "driver/rs232.h" |
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12 | #include "util/delay.h" |
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13 | |
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14 | |
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15 | ISR ( USART_RXC_vect ) { |
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16 | } |
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17 | |
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18 | void solenoid_delay(void) { |
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19 | _delay_ms(2); |
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20 | } |
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21 | |
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22 | |
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23 | // TODO: TYPE should be configured somewhere else |
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24 | #define TRACKSWITCH_TYPE 1 // 1=double, 2=single left, 3=single right, 4=pitlane |
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25 | #define TYPE_DOUBLE 1 |
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26 | #define TYPE_SINGLE_L 2 |
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27 | #define TYPE_SINGLE_R 3 |
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28 | #define TYPE_PITLANE 4 |
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29 | |
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30 | |
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31 | #define PULSE_PORT PORTD |
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32 | #define PULSE_BIT PD2 |
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33 | |
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34 | #define RESPONSE_PORT PORTC |
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35 | #define RESPONSE_PIN PC1 |
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36 | |
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37 | #define SOLENOID_A_PORT PORTB |
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38 | #define SOLENOID_B_PORT PORTB |
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39 | |
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40 | #ifdef WE_HAVE_TO_REVERSE_PORTS_ON_DOUBLE_SWITCH |
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41 | //#if (TRACKSWITCH_TYPE == TYPE_DOUBLE) |
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42 | // switch outputs - note: car0+1 have also be swapped! |
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43 | // todo in future |
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44 | #define SOLENOID_A_PIN PB2 |
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45 | #define SOLENOID_B_PIN PB1 |
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46 | #else |
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47 | #define SOLENOID_A_PIN PB1 |
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48 | #define SOLENOID_B_PIN PB2 |
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49 | #endif |
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50 | |
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51 | // internal analog comparator doesnt work well |
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52 | //#define ANALOG_COMPARATOR 1 |
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53 | |
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54 | volatile uint16_t data = 0; |
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55 | volatile uint8_t data_len = 0; |
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56 | volatile uint8_t bitbuf_len = 0; |
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57 | volatile uint16_t bitbuf = 0; |
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58 | volatile uint8_t car_speed[8]; |
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59 | volatile uint8_t car_switch[8]; |
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60 | volatile uint16_t car0, car1; |
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61 | volatile uint16_t car0_new, car0_old; |
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62 | volatile uint16_t car1_new, car1_old; |
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63 | |
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64 | volatile uint8_t response = 0; |
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65 | uint8_t self_id = 2; // TODO - muss ermittelt werden und systemweit eindeutig sein |
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66 | |
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67 | void send_response(uint16_t data) { |
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68 | /* frame format: |
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69 | 1 startbit |
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70 | 2 car id |
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71 | 3 car id |
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72 | 4 car id |
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73 | 5 track change status bit 1 |
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74 | 6 track change status bit 2 |
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75 | 7 sender id |
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76 | 8 sender id |
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77 | 9 sender id |
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78 | 9 sender id |
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79 | 10 device type |
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80 | 11 device type |
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81 | 12 device type |
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82 | 13 device type |
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83 | 14 reserved |
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84 | 15 reserved |
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85 | 16 stopbit |
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86 | */ |
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87 | uint8_t index = 16; // bit count maximum |
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88 | uint8_t enable = DDR(RESPONSE_PORT) | _BV(RESPONSE_PIN); |
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89 | uint8_t disable = DDR(RESPONSE_PORT) & ~_BV(RESPONSE_PIN); |
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90 | data |= 0b100000000000001; // make sure start/stop bits are set |
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91 | while (index != 0) { |
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92 | if ((data & 1) != 0) { |
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93 | DDR(RESPONSE_PORT) = enable; // enable response output |
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94 | } else { |
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95 | DDR(RESPONSE_PORT) = disable; // disable response output |
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96 | } |
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97 | data = data >> 1; // next bit prepare |
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98 | index--; // decrement index |
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99 | _delay_us(49); // bit valid phase |
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100 | } |
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101 | // finally be sure to release the bus! |
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102 | DDR(RESPONSE_PORT) = disable; // disable response output |
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103 | } |
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104 | |
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105 | |
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106 | ISR ( INT0_vect ) { |
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107 | GICR &= ~_BV(INT0) ; // Disable INT0 |
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108 | // Startsignal erkannt, ab hier den Timer2 starten, |
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109 | // der liest dann alle 50µs den Zustand ein und schreibt das |
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110 | // empfangene Bit in den Puffer |
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111 | bitbuf = 0; // init |
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112 | bitbuf_len = 0b10000000; // init 1 pulse received |
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113 | TCNT2 = 0; |
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114 | TIMSK |= _BV(OCIE2); //enable timer2 interrupt |
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115 | } |
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116 | |
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117 | ISR ( TIMER2_COMP_vect ) { |
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118 | uint8_t clock; |
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119 | uint8_t state; |
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120 | uint8_t state2; |
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121 | if ((bitbuf_len & 0b10000000) == 0) clock = 0; else clock = 0xff; |
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122 | if ((bitbuf_len & 0b01000000) == 0) state = 0; else state = 0xff; |
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123 | if ((PIN(PULSE_PORT) & _BV(PULSE_BIT)) == 0) state2 = 0xff; else state2 = 0; |
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124 | |
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125 | if (clock) { |
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126 | bitbuf_len &= ~_BV(7); // switch clock to low |
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127 | // second pulse of bit |
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128 | if ((state==state2) & state2) { |
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129 | // two cycles high: packet end received |
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130 | data_len = (bitbuf_len & 0b00111111); |
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131 | TIMSK &= ~_BV(OCIE2); //disable timer2 interrupt |
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132 | GICR |= _BV(INT0) ; // Enable INT0 |
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133 | |
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134 | //data = bitbuf; // output data |
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135 | // write data of controllers to array |
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136 | if (data_len == 10) { // controller data packet |
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137 | clock = (bitbuf >> 6) & 0b00000111; |
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138 | car_speed[clock] = (bitbuf >> 1) & 0x0F; |
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139 | car_switch[clock] = (bitbuf >> 5) & 1; |
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140 | // current response for this car? |
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141 | if (response != 0) { |
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142 | if ( ((response & 0b00001110) >> 1) == clock) { |
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143 | // add our ID to response: |
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144 | send_response(response | self_id << 6); |
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145 | response = 0; |
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146 | } |
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147 | } |
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148 | } |
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149 | |
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150 | |
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151 | } else { |
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152 | bitbuf_len++; // increment bit counter |
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153 | bitbuf = bitbuf << 1; // shift bits |
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154 | if (state2 == 0) bitbuf |= 1; // receive logic one |
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155 | } |
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156 | } else { |
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157 | bitbuf_len |= _BV(7); // switch clock to high |
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158 | // first pulse of bit |
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159 | if (state2) { |
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160 | bitbuf_len |= _BV(6); // store new state |
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161 | } else { |
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162 | bitbuf_len &= ~_BV(6); // store new state |
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163 | } |
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164 | } |
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165 | } |
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166 | |
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167 | |
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168 | ISR (TIMER1_OVF_vect) { |
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169 | // reset both car counters to overflow |
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170 | car0_old = 0xffff; |
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171 | car1_old = 0xffff; |
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172 | } |
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173 | |
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174 | ISR (INT1_vect) { |
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175 | // car0 detector |
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176 | uint16_t tmp = 0; |
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177 | car0_new = TCNT1; // get current counter |
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178 | if (car0_old < car0_new) { |
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179 | // calculate difference |
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180 | if (car0 == 0) tmp = car0_new-car0_old; |
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181 | if ( (tmp > 54) && (tmp < 74) ) car0 = 1; |
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182 | if ( (tmp > 118) && (tmp < 138) ) car0 = 2; |
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183 | if ( (tmp > 186) && (tmp < 206) ) car0 = 3; |
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184 | if ( (tmp > 246) && (tmp < 266) ) car0 = 4; |
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185 | if ( (tmp > 310) && (tmp < 330) ) car0 = 5; |
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186 | if ( (tmp > 374) && (tmp < 394) ) car0 = 6; |
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187 | } |
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188 | car0_old = car0_new; |
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189 | } |
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190 | |
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191 | // ISR (TIMER1_CAPT_vect) { |
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192 | #ifdef ANALOG_COMPARATOR |
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193 | ISR (ANA_COMP_vect) { |
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194 | // car1 detector |
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195 | uint16_t tmp = 0; |
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196 | car1_new = TCNT1; // get current counter |
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197 | if (car1_old < car1_new) { |
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198 | // calculate difference |
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199 | if (car1 == 0) tmp = car1_new-car1_old; |
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200 | if ( (tmp > 50) && (tmp < 78) ) car1 = 1; |
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201 | if ( (tmp > 114) && (tmp < 146) ) car1 = 2; |
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202 | if ( (tmp > 183) && (tmp < 210) ) car1 = 3; |
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203 | if ( (tmp > 242) && (tmp < 270) ) car1 = 4; |
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204 | if ( (tmp > 310) && (tmp < 330) ) car1 = 5; |
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205 | if ( (tmp > 374) && (tmp < 394) ) car1 = 6; |
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206 | } |
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207 | car1_old = car1_new; |
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208 | } |
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209 | #else |
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210 | // ALTERNATIV: |
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211 | ISR (TIMER1_CAPT_vect) { |
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212 | // car1 detector |
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213 | uint16_t tmp = 0; |
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214 | car1_new = TCNT1; // get current counter |
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215 | if (car1_old < car1_new) { |
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216 | // calculate difference |
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217 | if (car1 == 0) tmp = car1_new-car1_old; |
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218 | if ( (tmp > 50) && (tmp < 78) ) car1 = 1; |
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219 | if ( (tmp > 114) && (tmp < 146) ) car1 = 2; |
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220 | if ( (tmp > 183) && (tmp < 210) ) car1 = 3; |
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221 | if ( (tmp > 242) && (tmp < 270) ) car1 = 4; |
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222 | if ( (tmp > 310) && (tmp < 330) ) car1 = 5; |
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223 | if ( (tmp > 374) && (tmp < 394) ) car1 = 6; |
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224 | } |
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225 | car1_old = car1_new; |
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226 | } |
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227 | #endif |
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228 | |
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229 | |
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230 | |
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231 | |
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232 | |
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233 | int main(void) |
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234 | { |
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235 | uint8_t car0_state, car1_state; |
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236 | |
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237 | // setup data bit timer2 |
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238 | TCCR2 = (1<<CS21) | (1<<WGM21); //divide by 8, set compare match |
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239 | OCR2 = TIMER2_50US; |
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240 | |
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241 | // initialize timer1 for IR signal detection |
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242 | #ifdef ANALOG_COMPARATOR |
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243 | TCCR1B = _BV(CS01) ; // 1mhz clock |
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244 | TIMSK = _BV(OCIE2) | _BV(TOIE1) ; //enable timer1+2 |
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245 | #else |
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246 | TCCR1B = _BV(CS01) | _BV(ICNC1) | _BV(ICES1); // 1mhz clock, enable ICP on rising edge |
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247 | TIMSK = _BV(OCIE2) | _BV(TOIE1) | _BV(TICIE1); //enable timer1+2 / ICP1 |
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248 | #endif |
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249 | |
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250 | // enable both external interrupts |
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251 | // int 0 = data RX |
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252 | // int 1 = car0 input |
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253 | MCUCR = _BV(ISC00) | _BV(ISC01) | _BV(ISC10) | _BV(ISC11); // INT0/1 rising edge |
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254 | GICR = _BV(INT0) | _BV(INT1) ; // Enable INT0 + INT1 |
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255 | |
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256 | #ifdef ANALOG_COMPARATOR |
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257 | ACSR = _BV(ACIE) | _BV(ACIS1) | _BV(ACIS0); // setup analog comparator |
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258 | #endif |
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259 | |
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260 | // oscillator calibration |
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261 | // atmega8@1mhz = 0xac |
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262 | // @4mhz = ca 0xa0 |
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263 | //OSCCAL = 0xa0; |
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264 | //OSCCAL = 0x9A; |
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265 | //OSCCAL = 0xa0; // internal oscillator @ 4 mhz.... doesnt work accurate! |
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266 | |
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267 | RS232_init(); // initialize RS232 interface |
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268 | RS232_puts_p(PSTR("Freeslot TrackSwitch v1.3\n")); |
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269 | sei(); |
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270 | |
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271 | |
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272 | DDR(SOLENOID_A_PORT) |= _BV(SOLENOID_A_PIN); |
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273 | DDR(SOLENOID_B_PORT) |= _BV(SOLENOID_B_PIN); |
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274 | |
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275 | DDR(RESPONSE_PORT) &= ~_BV(RESPONSE_PIN); // switch response off |
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276 | RESPONSE_PORT &= ~_BV(RESPONSE_PIN); // switch response off |
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277 | |
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278 | while (1) { |
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279 | // main loop |
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280 | |
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281 | /* |
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282 | 0 = AA |
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283 | 1 = AB |
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284 | 2 = BB |
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285 | 3 = BA |
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286 | */ |
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287 | if (car0 != car0_state) { |
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288 | car0_state = car0; |
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289 | #if (TRACKSWITCH_TYPE == TYPE_DOUBLE) || (TRACKSWITCH_TYPE == TYPE_SINGLE_R) |
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290 | if ( (car0_state != 0) && (car_switch[car0_state-1] == 0) && (car_speed[car0_state-1]>0) ) { |
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291 | response = (1 | ((car0_state-1)<<1) | (1 << 4)); |
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292 | // trigger solenoid A |
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293 | RS232_putc('A'); |
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294 | RS232_putc('B'); |
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295 | RS232_putc('0'+car0_state); |
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296 | RS232_putc('\n'); |
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297 | |
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298 | SOLENOID_A_PORT |= _BV(SOLENOID_A_PIN); |
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299 | solenoid_delay(); |
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300 | SOLENOID_A_PORT &= ~_BV(SOLENOID_A_PIN); |
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301 | solenoid_delay(); |
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302 | } else |
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303 | #endif |
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304 | if (car0_state != 0) { |
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305 | response = (1 | ((car0_state-1)<<1)); |
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306 | RS232_putc('A'); |
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307 | RS232_putc('A'); |
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308 | RS232_putc('0'+car0_state); |
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309 | RS232_putc('\n'); |
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310 | } |
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311 | } car0 = 0; |
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312 | |
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313 | |
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314 | if (car1 != car1_state) { |
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315 | car1_state = car1; |
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316 | #if (TRACKSWITCH_TYPE == TYPE_DOUBLE) || (TRACKSWITCH_TYPE == TYPE_SINGLE_L) |
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317 | if ( (car1_state != 0) && (car_switch[car1_state-1] == 0) && (car_speed[car1_state-1]>0) ) { |
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318 | response = (1 | ((car1_state-1)<<1) | (3 << 4)); |
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319 | // trigger solenoid B |
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320 | RS232_putc('B'); |
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321 | RS232_putc('A'); |
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322 | RS232_putc('0'+car1_state); |
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323 | RS232_putc('\n'); |
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324 | |
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325 | SOLENOID_B_PORT |= _BV(SOLENOID_B_PIN); |
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326 | solenoid_delay(); |
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327 | SOLENOID_B_PORT &= ~_BV(SOLENOID_B_PIN); |
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328 | solenoid_delay(); |
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329 | } else |
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330 | #endif |
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331 | if (car1_state != 0) { |
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332 | response = (1 | ((car1_state-1)<<1) | (2 << 4)); |
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333 | RS232_putc('B'); |
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334 | RS232_putc('B'); |
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335 | RS232_putc('0'+car1_state); |
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336 | RS232_putc('\n'); |
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337 | } |
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338 | } car1 = 0; |
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339 | |
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340 | |
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341 | } // main loop end |
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342 | }; |
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343 |