trackswitch/main.c

Sat, 10 Dec 2011 10:51:24 +0100

author
Malte Bayer <mbayer@neo-soft.org>
date
Sat, 10 Dec 2011 10:51:24 +0100
changeset 68
c3460121ad8b
parent 62
66dd5763dfb3
child 69
27c0c0095e26
permissions
-rw-r--r--

fix: pitlane response missing

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1 #include <avr/interrupt.h>
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2 #include <avr/io.h>
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3 #include <avr/wdt.h>
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4 #include <avr/eeprom.h>
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5 #include <stdlib.h>
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6 #include <stdint.h>
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7 #include <avr/pgmspace.h>
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8
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9 #include "main.h"
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10
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11 #include "driver/rs232.h"
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12 #include "util/delay.h"
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15 ISR ( USART_RXC_vect ) {
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16 }
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17
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18 #define PULSE_PORT PORTD
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19 #define PULSE_BIT PD2
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20 #define RESPONSE_PORT PORTD
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21 #define RESPONSE_PIN PD5
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22 #define SOLENOID_A_PORT PORTB
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23 #define SOLENOID_B_PORT PORTB
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24
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25 #define TRACKSWITCH_TYPE 2 // 1=double, 2=single
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26
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27 #define SOLENOID_A_PIN PB1
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28 #define SOLENOID_B_PIN PB2
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29
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30 // internal analog comparator doesnt work well
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31 //#define ANALOG_COMPARATOR 1
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32
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33 volatile uint16_t data = 0;
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34 volatile uint8_t data_len = 0;
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35 volatile uint8_t bitbuf_len = 0;
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36 volatile uint16_t bitbuf = 0;
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37 volatile uint8_t car_speed[8];
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38 volatile uint8_t car_switch[8];
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39 volatile uint16_t car0, car1;
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40 volatile uint16_t car0_new, car0_old;
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41 volatile uint16_t car1_new, car1_old;
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42
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43 volatile uint8_t response = 0;
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44 uint8_t self_id = 2; // TODO - muss ermittelt werden und systemweit eindeutig sein
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45
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46 void send_response(uint16_t data) {
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47 /* frame format:
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48 1 startbit
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49 2 car id
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50 3 car id
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51 4 car id
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52 5 track change status bit 1
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53 6 track change status bit 2
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54 7 sender id
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55 8 sender id
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56 9 sender id
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57 9 sender id
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58 10 device type
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59 11 device type
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60 12 device type
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61 13 device type
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62 14 reserved
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63 15 reserved
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64 16 stopbit
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65 */
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66 uint8_t index = 16; // bit count maximum
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67 uint8_t enable = DDR(RESPONSE_PORT) | _BV(RESPONSE_PIN);
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68 uint8_t disable = DDR(RESPONSE_PORT) & ~_BV(RESPONSE_PIN);
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69 data |= 0b100000000000001; // make sure start/stop bits are set
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70 data = 0b1010101010101011;
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71 while (index != 0) {
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72 if ((data & 1) != 0) {
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73 DDR(RESPONSE_PORT) = enable; // enable response output
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74 } else {
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75 DDR(RESPONSE_PORT) = disable; // disable response output
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76 }
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77 data = data >> 1; // next bit prepare
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78 index--; // decrement index
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79 _delay_us(49); // bit valid phase
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80 }
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81 // finally be sure to release the bus!
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82 DDR(RESPONSE_PORT) = disable; // disable response output
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83 }
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84
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85
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86 ISR ( INT0_vect ) {
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87 GICR &= ~_BV(INT0) ; // Disable INT0
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88 // Startsignal erkannt, ab hier den Timer2 starten,
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89 // der liest dann alle 50µs den Zustand ein und schreibt das
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90 // empfangene Bit in den Puffer
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91 bitbuf = 0; // init
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92 bitbuf_len = 0b10000000; // init 1 pulse received
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93 TCNT2 = 0;
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94 TIMSK |= _BV(OCIE2); //enable timer2 interrupt
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95 }
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96
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97 ISR ( TIMER2_COMP_vect ) {
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98 uint8_t clock;
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99 uint8_t state;
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100 uint8_t state2;
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101 if ((bitbuf_len & 0b10000000) == 0) clock = 0; else clock = 0xff;
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102 if ((bitbuf_len & 0b01000000) == 0) state = 0; else state = 0xff;
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103 if ((PIN(PULSE_PORT) & _BV(PULSE_BIT)) == 0) state2 = 0xff; else state2 = 0;
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104
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105 if (clock) {
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106 bitbuf_len &= ~_BV(7); // switch clock to low
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107 // second pulse of bit
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108 if ((state==state2) & state2) {
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109 // two cycles high: packet end received
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110 data_len = (bitbuf_len & 0b00111111);
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111 TIMSK &= ~_BV(OCIE2); //disable timer2 interrupt
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112 GICR |= _BV(INT0) ; // Enable INT0
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113
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114 //data = bitbuf; // output data
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115 // write data of controllers to array
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116 if (data_len == 10) { // controller data packet
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117 clock = (bitbuf >> 6) & 0b00000111;
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118 car_speed[clock] = (bitbuf >> 1) & 0x0F;
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119 car_switch[clock] = (bitbuf >> 5) & 1;
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120 // current response for this car?
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121 if (response != 0) {
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122 if ( ((response & 0b00001110) >> 1) == clock) {
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123 // add our ID to response:
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124 send_response(response | self_id << 6);
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125 response = 0;
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126 }
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127 }
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128 }
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129
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130
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131 } else {
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132 bitbuf_len++; // increment bit counter
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133 bitbuf = bitbuf << 1; // shift bits
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134 if (state2 == 0) bitbuf |= 1; // receive logic one
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135 }
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136 } else {
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137 bitbuf_len |= _BV(7); // switch clock to high
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138 // first pulse of bit
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139 if (state2) {
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140 bitbuf_len |= _BV(6); // store new state
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141 } else {
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142 bitbuf_len &= ~_BV(6); // store new state
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143 }
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144 }
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145 }
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146
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147
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148 ISR (TIMER1_OVF_vect) {
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149 // reset both car counters to overflow
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150 car0_old = 0xffff;
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151 car1_old = 0xffff;
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152 }
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153
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154 ISR (INT1_vect) {
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155 // car0 detector
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156 uint16_t tmp = 0;
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157 car0_new = TCNT1; // get current counter
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158 if (car0_old < car0_new) {
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159 // calculate difference
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160 if (car0 == 0) tmp = car0_new-car0_old;
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161 if ( (tmp > 54) && (tmp < 74) ) car0 = 1;
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162 if ( (tmp > 118) && (tmp < 138) ) car0 = 2;
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163 if ( (tmp > 186) && (tmp < 206) ) car0 = 3;
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164 if ( (tmp > 246) && (tmp < 266) ) car0 = 4;
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165 if ( (tmp > 310) && (tmp < 330) ) car0 = 5;
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166 if ( (tmp > 374) && (tmp < 394) ) car0 = 6;
19
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167 }
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168 car0_old = car0_new;
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169 }
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170
21
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171 // ISR (TIMER1_CAPT_vect) {
22
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172 #ifdef ANALOG_COMPARATOR
21
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173 ISR (ANA_COMP_vect) {
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174 // car1 detector
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175 uint16_t tmp = 0;
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176 car1_new = TCNT1; // get current counter
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177 if (car1_old < car1_new) {
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178 // calculate difference
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179 if (car1 == 0) tmp = car1_new-car1_old;
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180 if ( (tmp > 50) && (tmp < 78) ) car1 = 1;
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181 if ( (tmp > 114) && (tmp < 146) ) car1 = 2;
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182 if ( (tmp > 183) && (tmp < 210) ) car1 = 3;
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183 if ( (tmp > 242) && (tmp < 270) ) car1 = 4;
62
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184 if ( (tmp > 310) && (tmp < 330) ) car1 = 5;
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185 if ( (tmp > 374) && (tmp < 394) ) car1 = 6;
21
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186 }
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187 car1_old = car1_new;
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188 }
22
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189 #else
21
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190 // ALTERNATIV:
19
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191 ISR (TIMER1_CAPT_vect) {
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192 // car1 detector
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193 uint16_t tmp = 0;
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194 car1_new = TCNT1; // get current counter
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195 if (car1_old < car1_new) {
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196 // calculate difference
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197 if (car1 == 0) tmp = car1_new-car1_old;
21
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198 if ( (tmp > 50) && (tmp < 78) ) car1 = 1;
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199 if ( (tmp > 114) && (tmp < 146) ) car1 = 2;
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200 if ( (tmp > 183) && (tmp < 210) ) car1 = 3;
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201 if ( (tmp > 242) && (tmp < 270) ) car1 = 4;
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202 if ( (tmp > 310) && (tmp < 330) ) car1 = 5;
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203 if ( (tmp > 374) && (tmp < 394) ) car1 = 6;
19
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204 }
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205 car1_old = car1_new;
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206 }
22
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207 #endif
20
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208
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209 void solenoid_delay(void) {
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210 _delay_ms(10);
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211 }
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212
19
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213
21
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214
40
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215
19
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216 int main(void)
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217 {
20
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218 uint8_t car0_state, car1_state;
19
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219
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220 // setup data bit timer2
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221 TCCR2 = (1<<CS21) | (1<<WGM21); //divide by 8, set compare match
20
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222 OCR2 = TIMER2_50US;
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223
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224 // initialize timer1 for IR signal detection
21
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225 #ifdef ANALOG_COMPARATOR
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226 TCCR1B = _BV(CS01) ; // 1mhz clock
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227 TIMSK = _BV(OCIE2) | _BV(TOIE1) ; //enable timer1+2
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228 #else
19
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229 TCCR1B = _BV(CS01) | _BV(ICNC1) | _BV(ICES1); // 1mhz clock, enable ICP on rising edge
21
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230 TIMSK = _BV(OCIE2) | _BV(TOIE1) | _BV(TICIE1); //enable timer1+2 / ICP1
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231 #endif
19
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232
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233 // enable both external interrupts
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234 // int 0 = data RX
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235 // int 1 = car0 input
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236 MCUCR = _BV(ISC00) | _BV(ISC01) | _BV(ISC10) | _BV(ISC11); // INT0/1 rising edge
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237 GICR = _BV(INT0) | _BV(INT1) ; // Enable INT0 + INT1
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238
21
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239 #ifdef ANALOG_COMPARATOR
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240 ACSR = _BV(ACIE) | _BV(ACIS1) | _BV(ACIS0); // setup analog comparator
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241 #endif
19
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242
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243 // oscillator calibration
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244 // atmega8@1mhz = 0xac
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245 // @4mhz = ca 0xa0
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246 //OSCCAL = 0xa0;
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247 //OSCCAL = 0x9A;
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248 //OSCCAL = 0xa0; // internal oscillator @ 4 mhz.... doesnt work accurate!
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249
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250 RS232_init(); // initialize RS232 interface
40
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251 RS232_puts_p(PSTR("Freeslot TrackSwitch v1.2\n"));
19
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252 sei();
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253
21
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254
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255 DDR(SOLENOID_A_PORT) |= _BV(SOLENOID_A_PIN);
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256 DDR(SOLENOID_B_PORT) |= _BV(SOLENOID_B_PIN);
19
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257
40
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diff changeset
258 DDR(RESPONSE_PORT) &= ~_BV(RESPONSE_PIN); // switch response off
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259 RESPONSE_PORT &= ~_BV(RESPONSE_PIN); // switch response off
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diff changeset
260
19
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261 while (1) {
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262 // main loop
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263
40
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diff changeset
264 /*
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diff changeset
265 0 = AA
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266 1 = AB
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267 2 = BB
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268 3 = BA
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269 */
20
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diff changeset
270 if (car0 != car0_state) {
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271 car0_state = car0;
22
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diff changeset
272 if ( (car0_state != 0) && (car_switch[car0_state-1] == 0) && (car_speed[car0_state-1]>0) ) {
40
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diff changeset
273 response = (1 | ((car0_state-1)<<1) | (1 << 4));
20
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diff changeset
274 // trigger solenoid A
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275 RS232_putc('A');
22
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276 RS232_putc('B');
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277 RS232_putc('0'+car0_state);
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278 RS232_putc('\n');
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279
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280 SOLENOID_A_PORT |= _BV(SOLENOID_A_PIN);
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281 solenoid_delay();
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282 SOLENOID_A_PORT &= ~_BV(SOLENOID_A_PIN);
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283 solenoid_delay();
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284 }
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285 if (car0_state != 0) {
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286 response = (1 | ((car0_state-1)<<1));
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287 RS232_putc('A');
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288 RS232_putc('A');
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289 RS232_putc('0'+car0_state);
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290 RS232_putc('\n');
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291 }
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292 } car0 = 0;
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293
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294
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295 if (car1 != car1_state) {
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296 car1_state = car1;
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297 if ( (car1_state != 0) && (car_switch[car1_state-1] == 0) && (car_speed[car1_state-1]>0) ) {
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298 response = (1 | ((car1_state-1)<<1) | (3 << 4));
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299 // trigger solenoid B
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300 RS232_putc('B');
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301 RS232_putc('A');
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302 RS232_putc('0'+car1_state);
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303 RS232_putc('\n');
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304
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305 SOLENOID_B_PORT |= _BV(SOLENOID_B_PIN);
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306 solenoid_delay();
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307 SOLENOID_B_PORT &= ~_BV(SOLENOID_B_PIN);
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308 solenoid_delay();
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309 }
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310 if (car1_state != 0) {
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311 response = (1 | ((car1_state-1)<<1) | (2 << 4));
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312 RS232_putc('B');
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313 RS232_putc('B');
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314 RS232_putc('0'+car1_state);
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315 RS232_putc('\n');
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316 }
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317 } car1 = 0;
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318
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319
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320 } // main loop end
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321 };
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322

mercurial