Sat, 03 Dec 2011 09:16:39 +0100
added some communication definitions
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1 | #include <avr/interrupt.h> |
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2 | #include <avr/io.h> |
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3 | #include <avr/wdt.h> |
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4 | #include <avr/eeprom.h> |
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5 | #include <stdlib.h> |
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6 | #include <stdint.h> |
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7 | #include <avr/pgmspace.h> |
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8 | |
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9 | #include "main.h" |
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10 | |
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11 | #include "driver/rs232.h" |
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12 | #include "util/delay.h" |
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13 | |
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14 | |
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15 | ISR ( USART_RXC_vect ) { |
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16 | } |
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17 | |
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18 | #define PULSE_PORT PORTD |
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19 | #define PULSE_BIT PD2 |
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20 | #define SOLENOID_A_PORT PORTB |
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21 | #define SOLENOID_B_PORT PORTB |
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22 | |
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23 | #define TRACKSWITCH_TYPE 2 // 1=double, 2=single |
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24 | |
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25 | #define SOLENOID_A_PIN PB1 |
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26 | #define SOLENOID_B_PIN PB2 |
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27 | |
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28 | // internal analog comparator doesnt work well |
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29 | //#define ANALOG_COMPARATOR 1 |
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30 | |
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31 | volatile uint16_t data = 0; |
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32 | volatile uint8_t data_len = 0; |
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33 | volatile uint8_t bitbuf_len = 0; |
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34 | volatile uint16_t bitbuf = 0; |
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35 | volatile uint8_t car_speed[8]; |
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36 | volatile uint8_t car_switch[8]; |
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37 | volatile uint16_t car0, car1; |
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38 | volatile uint16_t car0_new, car0_old; |
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39 | volatile uint16_t car1_new, car1_old; |
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40 | |
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41 | ISR ( INT0_vect ) { |
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42 | GICR &= ~_BV(INT0) ; // Disable INT0 |
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43 | // Startsignal erkannt, ab hier den Timer2 starten, |
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44 | // der liest dann alle 50µs den Zustand ein und schreibt das |
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45 | // empfangene Bit in den Puffer |
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46 | bitbuf = 0; // init |
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47 | bitbuf_len = 0b10000000; // init 1 pulse received |
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48 | TCNT2 = 0; |
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49 | TIMSK |= _BV(OCIE2); //enable timer2 interrupt |
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50 | } |
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51 | |
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52 | ISR ( TIMER2_COMP_vect ) { |
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53 | uint8_t clock; |
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54 | uint8_t state; |
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55 | uint8_t state2; |
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56 | if ((bitbuf_len & 0b10000000) == 0) clock = 0; else clock = 0xff; |
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57 | if ((bitbuf_len & 0b01000000) == 0) state = 0; else state = 0xff; |
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58 | if ((PIN(PULSE_PORT) & _BV(PULSE_BIT)) == 0) state2 = 0xff; else state2 = 0; |
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59 | |
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60 | if (clock) { |
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61 | bitbuf_len &= ~_BV(7); // switch clock to low |
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62 | // second pulse of bit |
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63 | if ((state==state2) & state2) { |
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64 | // two cycles high: packet end received |
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65 | data_len = (bitbuf_len & 0b00111111); |
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66 | TIMSK &= ~_BV(OCIE2); //disable timer2 interrupt |
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67 | GICR |= _BV(INT0) ; // Enable INT0 |
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68 | |
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69 | //data = bitbuf; // output data |
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70 | // write data of controllers to array |
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71 | if (data_len == 10) { // controller data packet |
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72 | clock = (bitbuf >> 6) & 0b00000111; |
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73 | car_speed[clock] = (bitbuf >> 1) & 0x0F; |
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74 | car_switch[clock] = (bitbuf >> 5) & 1; |
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75 | } |
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76 | |
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77 | |
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78 | } else { |
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79 | bitbuf_len++; // increment bit counter |
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80 | bitbuf = bitbuf << 1; // shift bits |
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81 | if (state2 == 0) bitbuf |= 1; // receive logic one |
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82 | } |
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83 | } else { |
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84 | bitbuf_len |= _BV(7); // switch clock to high |
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85 | // first pulse of bit |
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86 | if (state2) { |
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87 | bitbuf_len |= _BV(6); // store new state |
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88 | } else { |
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89 | bitbuf_len &= ~_BV(6); // store new state |
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90 | } |
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91 | } |
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92 | } |
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93 | |
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94 | |
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95 | ISR (TIMER1_OVF_vect) { |
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96 | // reset both car counters to overflow |
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97 | car0_old = 0xffff; |
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98 | car1_old = 0xffff; |
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99 | } |
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100 | |
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101 | ISR (INT1_vect) { |
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102 | // car0 detector |
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103 | uint16_t tmp = 0; |
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104 | car0_new = TCNT1; // get current counter |
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105 | if (car0_old < car0_new) { |
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106 | // calculate difference |
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107 | if (car0 == 0) tmp = car0_new-car0_old; |
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108 | if ( (tmp > 54) && (tmp < 74) ) car0 = 1; |
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109 | if ( (tmp > 118) && (tmp < 138) ) car0 = 2; |
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110 | if ( (tmp > 186) && (tmp < 206) ) car0 = 3; |
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111 | if ( (tmp > 246) && (tmp < 266) ) car0 = 4; |
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112 | } |
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113 | car0_old = car0_new; |
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114 | } |
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115 | |
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116 | // ISR (TIMER1_CAPT_vect) { |
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117 | #ifdef ANALOG_COMPARATOR |
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118 | ISR (ANA_COMP_vect) { |
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119 | // car1 detector |
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120 | uint16_t tmp = 0; |
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121 | car1_new = TCNT1; // get current counter |
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122 | if (car1_old < car1_new) { |
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123 | // calculate difference |
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124 | if (car1 == 0) tmp = car1_new-car1_old; |
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125 | if ( (tmp > 50) && (tmp < 78) ) car1 = 1; |
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126 | if ( (tmp > 114) && (tmp < 146) ) car1 = 2; |
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127 | if ( (tmp > 183) && (tmp < 210) ) car1 = 3; |
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128 | if ( (tmp > 242) && (tmp < 270) ) car1 = 4; |
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129 | } |
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130 | car1_old = car1_new; |
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131 | } |
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132 | #else |
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133 | // ALTERNATIV: |
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134 | ISR (TIMER1_CAPT_vect) { |
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135 | // car1 detector |
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136 | uint16_t tmp = 0; |
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137 | car1_new = TCNT1; // get current counter |
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138 | if (car1_old < car1_new) { |
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139 | // calculate difference |
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140 | if (car1 == 0) tmp = car1_new-car1_old; |
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141 | if ( (tmp > 50) && (tmp < 78) ) car1 = 1; |
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142 | if ( (tmp > 114) && (tmp < 146) ) car1 = 2; |
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143 | if ( (tmp > 183) && (tmp < 210) ) car1 = 3; |
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144 | if ( (tmp > 242) && (tmp < 270) ) car1 = 4; |
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145 | } |
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146 | car1_old = car1_new; |
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147 | } |
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148 | #endif |
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149 | |
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150 | void solenoid_delay(void) { |
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151 | _delay_ms(10); |
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152 | } |
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153 | |
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154 | |
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155 | |
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156 | int main(void) |
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157 | { |
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158 | uint8_t car0_state, car1_state; |
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159 | |
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160 | // setup data bit timer2 |
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161 | TCCR2 = (1<<CS21) | (1<<WGM21); //divide by 8, set compare match |
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162 | OCR2 = TIMER2_50US; |
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163 | |
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164 | // initialize timer1 for IR signal detection |
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165 | #ifdef ANALOG_COMPARATOR |
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166 | TCCR1B = _BV(CS01) ; // 1mhz clock |
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167 | TIMSK = _BV(OCIE2) | _BV(TOIE1) ; //enable timer1+2 |
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168 | #else |
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169 | TCCR1B = _BV(CS01) | _BV(ICNC1) | _BV(ICES1); // 1mhz clock, enable ICP on rising edge |
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170 | TIMSK = _BV(OCIE2) | _BV(TOIE1) | _BV(TICIE1); //enable timer1+2 / ICP1 |
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171 | #endif |
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172 | |
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173 | // enable both external interrupts |
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174 | // int 0 = data RX |
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175 | // int 1 = car0 input |
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176 | MCUCR = _BV(ISC00) | _BV(ISC01) | _BV(ISC10) | _BV(ISC11); // INT0/1 rising edge |
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177 | GICR = _BV(INT0) | _BV(INT1) ; // Enable INT0 + INT1 |
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178 | |
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179 | #ifdef ANALOG_COMPARATOR |
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180 | ACSR = _BV(ACIE) | _BV(ACIS1) | _BV(ACIS0); // setup analog comparator |
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181 | #endif |
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182 | |
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183 | // oscillator calibration |
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184 | // atmega8@1mhz = 0xac |
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185 | // @4mhz = ca 0xa0 |
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186 | //OSCCAL = 0xa0; |
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187 | //OSCCAL = 0x9A; |
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188 | //OSCCAL = 0xa0; // internal oscillator @ 4 mhz.... doesnt work accurate! |
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189 | |
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190 | RS232_init(); // initialize RS232 interface |
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191 | RS232_puts_p(PSTR("Freeslot TrackSwitch v1.1\n")); |
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192 | sei(); |
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193 | |
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194 | |
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195 | DDR(SOLENOID_A_PORT) |= _BV(SOLENOID_A_PIN); |
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196 | DDR(SOLENOID_B_PORT) |= _BV(SOLENOID_B_PIN); |
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197 | |
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198 | while (1) { |
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199 | // main loop |
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200 | |
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201 | if (car0 != car0_state) { |
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202 | car0_state = car0; |
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203 | if ( (car0_state != 0) && (car_switch[car0_state-1] == 0) && (car_speed[car0_state-1]>0) ) { |
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204 | // trigger solenoid A |
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205 | RS232_putc('A'); |
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206 | RS232_putc('B'); |
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207 | RS232_putc('0'+car0_state); |
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208 | RS232_putc('\n'); |
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209 | |
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210 | SOLENOID_A_PORT |= _BV(SOLENOID_A_PIN); |
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211 | solenoid_delay(); |
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212 | SOLENOID_A_PORT &= ~_BV(SOLENOID_A_PIN); |
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213 | solenoid_delay(); |
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214 | } |
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215 | if (car0_state != 0) { |
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216 | RS232_putc('A'); |
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217 | RS232_putc('A'); |
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218 | RS232_putc('0'+car0_state); |
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219 | RS232_putc('\n'); |
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220 | } |
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221 | } car0 = 0; |
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222 | |
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223 | |
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224 | if (car1 != car1_state) { |
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225 | car1_state = car1; |
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226 | if ( (car1_state != 0) && (car_switch[car1_state-1] == 0) && (car_speed[car1_state-1]>0) ) { |
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227 | // trigger solenoid A |
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228 | RS232_putc('B'); |
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229 | RS232_putc('A'); |
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230 | RS232_putc('0'+car1_state); |
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231 | RS232_putc('\n'); |
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232 | |
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233 | SOLENOID_B_PORT |= _BV(SOLENOID_B_PIN); |
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234 | solenoid_delay(); |
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235 | SOLENOID_B_PORT &= ~_BV(SOLENOID_B_PIN); |
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236 | solenoid_delay(); |
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237 | } |
22
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238 | if (car1_state != 0) { |
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239 | RS232_putc('B'); |
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240 | RS232_putc('B'); |
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241 | RS232_putc('0'+car1_state); |
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242 | RS232_putc('\n'); |
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243 | } |
20
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244 | } car1 = 0; |
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245 | |
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246 | |
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247 | } // main loop end |
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248 | }; |
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249 |