Mon, 14 Nov 2011 21:38:00 +0100
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1 | #ifndef MAIN_H |
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2 | #define MAIN_H |
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3 | |
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4 | #include <avr/wdt.h> |
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5 | #include <stdint.h> |
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6 | |
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7 | // Hardware config |
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8 | #define LAP_COUNTER_PORT PORTB |
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9 | #define LAP_COUNTER PB2 |
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10 | |
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11 | #define MODUL_PORT PORTD |
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12 | #define MODUL_ST4 PD5 |
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13 | #define MODUL_ST6 PD6 |
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14 | |
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15 | #define I2C_PORT PORTC |
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16 | #define I2C_SDA PC0 |
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17 | #define I2C_SCL PC1 |
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18 | |
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19 | #define LED1_PORT PORTA |
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20 | #define LED2_PORT PORTA |
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21 | #define LED3_PORT PORTC |
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22 | #define LED4_PORT PORTC |
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23 | #define LED5_PORT PORTC |
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24 | #define LED1 PA4 |
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25 | #define LED2 PA5 |
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26 | #define LED3 PC7 |
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27 | #define LED4 PC2 |
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28 | #define LED5 PC3 |
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29 | |
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30 | #define SW_PACECAR_PORT PORTC |
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31 | #define SW_START_PORT PORTB |
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32 | #define SW_FUEL_PORT PORTB |
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33 | #define SW_PACECAR PC6 |
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34 | #define SW_FUEL PB0 |
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35 | #define SW_START PB1 |
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36 | |
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37 | #define SPEAKER_PORT PORTD |
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38 | #define SPEAKER PD7 |
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39 | |
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40 | #define RAIL_POWER_PORT PORTD |
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41 | #define RAIL_POWER PD4 // high = rails powered |
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42 | #define RAIL_DETECT_PORT PORTA |
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43 | #define RAIL_DETECT PA7 // low = short circuit detection |
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44 | |
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45 | #define CONTROLLER_PORT PORTB |
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46 | #define CONTROLLER_MAX 360 // full throttle ADC value |
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47 | #define CONTROLLER_DIVISOR (uint8_t)(CONTROLLER_MAX/15) |
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48 | #define CONTROLLER1_SW 4 |
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49 | #define CONTROLLER2_SW 5 |
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50 | #define CONTROLLER3_SW 6 |
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51 | #define CONTROLLER4_SW 7 |
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52 | #define CONTROLLER1_SPEED 0 // ADC channel # |
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53 | #define CONTROLLER2_SPEED 1 // ADC channel # |
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54 | #define CONTROLLER3_SPEED 2 // ADC channel # |
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55 | #define CONTROLLER4_SPEED 3 // ADC channel # |
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56 | |
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57 | // TIMING STUFF |
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58 | /* |
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59 | #define TIMER0_DIVISOR 8 |
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60 | #define VALUE_50US 0.45e-4 |
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61 | #define TIMER_50US 0xff - (uint8_t)(VALUE_50US * F_CPU/TIMER0_DIVISOR) |
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62 | */ |
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63 | /* |
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64 | #define VALUE_7500NS 0.85e-2 |
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65 | #define TIMER_7500NS 0xffff - (uint16_t)(VALUE_7500NS * F_CPU/TIMER1_DIVISOR) |
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66 | */ |
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67 | //#define TIMER_7500NS (uint16_t)(VALUE_7500NS * F_CPU/TIMER1_DIVISOR) |
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68 | #define TIMER2_DIVISOR 8 |
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69 | #define VALUE2_50US 0.50e-4 |
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70 | #define TIMER2_50US (uint8_t)(VALUE2_50US * F_CPU/TIMER2_DIVISOR) |
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71 | |
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72 | #define TIMER1_DIVISOR 8 |
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73 | #define VALUE1_7500NS 0.75e-2 |
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74 | #define TIMER1_7500NS (uint16_t)(VALUE1_7500NS * F_CPU/TIMER1_DIVISOR) |
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75 | |
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76 | |
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77 | #define DDR(x) (*(&x - 1)) // address of data direction register of port x |
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78 | #define PIN(x) (*(&x - 2)) // address of input register of port x |
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79 | |
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80 | |
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81 | |
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82 | // MAYBE USELESS STUFF: |
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83 | |
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84 | #define uchar unsigned char |
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85 | #define uint unsigned int |
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86 | |
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87 | // Macro used to write to a single I/O pin |
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88 | #define writeBit(port,bit,value) { if ((value)>0) (port) |= (1<<bit); else (port) &= ~(1<<bit); } |
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89 | |
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90 | // Macro used to read from a single I/O pin |
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91 | #define readBit(port,bit) (((port) >> (bit)) & 1) |
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92 | |
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93 | // we have internal AREF... |
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94 | // #define EXT_AREF 1 |
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95 | |
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96 | #endif |