Sat, 10 Dec 2011 16:37:55 +0100
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1 | #include <avr/interrupt.h> |
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2 | #include <avr/io.h> |
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3 | #include <avr/wdt.h> |
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4 | #include <avr/eeprom.h> |
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5 | #include <stdlib.h> |
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6 | #include <stdint.h> |
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7 | #include <avr/pgmspace.h> |
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8 | |
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9 | #include "main.h" |
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10 | |
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11 | #include "driver/rs232.h" |
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12 | #include "util/delay.h" |
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13 | |
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14 | |
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15 | ISR ( USART_RXC_vect ) { |
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16 | } |
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17 | |
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18 | #define PULSE_PORT PORTD |
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19 | #define PULSE_BIT PD2 |
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20 | #define RESPONSE_PORT PORTC |
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21 | #define RESPONSE_PIN PC1 |
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22 | #define SOLENOID_A_PORT PORTB |
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23 | #define SOLENOID_B_PORT PORTB |
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24 | #define SOLENOID_A_PIN PB1 |
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25 | #define SOLENOID_B_PIN PB2 |
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26 | |
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27 | #define TRACKSWITCH_TYPE 4 // 1=double, 2=single left, 3=single right, 4=pitlane |
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28 | #define TYPE_DOUBLE 1 |
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29 | #define TYPE_SINGLE_L 2 |
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30 | #define TYPE_SINGLE_R 3 |
67 | 31 | #define TYPE_PITLANE 4 |
32 | ||
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33 | #define MAX_SENSORS 3 |
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34 | |
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35 | #define PIT_PORT PORTC |
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36 | #define PIT_CONNECT_PIN PC3 |
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37 | #define PIT_GROUND_PIN PC2 // low active |
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38 | |
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39 | #define SENS2_PORT PORTD |
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40 | #define SENS2_PIN PD5 |
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41 | |
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42 | #define LED_PORT PORTB |
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43 | #define LED_PIN PB5 |
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44 | |
67 | 45 | |
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46 | // internal analog comparator doesnt work well |
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47 | //#define ANALOG_COMPARATOR 1 |
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48 | |
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49 | typedef struct { |
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50 | unsigned speed:4; |
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51 | unsigned trackswitch:1; |
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52 | unsigned inside:1; |
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53 | } cardata; |
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54 | |
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55 | typedef struct { |
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56 | unsigned car:4; |
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57 | unsigned state:4; |
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58 | uint16_t old, new; |
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59 | } sensordata; |
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60 | |
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61 | volatile cardata slot[MAX_SLOTS]; |
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62 | volatile sensordata sens[MAX_SENSORS]; |
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63 | |
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64 | volatile uint16_t data = 0; |
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65 | volatile uint8_t data_len = 0; |
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66 | volatile uint8_t bitbuf_len = 0; |
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67 | volatile uint16_t bitbuf = 0; |
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68 | |
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69 | volatile uint8_t response = 0; |
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70 | volatile uint8_t response_car = 0; |
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71 | uint8_t self_id = 0b1111; // ONLY ONE pitlane |
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72 | |
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73 | void solenoid_delay(void) { |
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74 | _delay_ms(2); |
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75 | } |
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76 | |
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77 | void send_response(uint8_t car, uint8_t status) { |
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78 | /* frame format: |
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79 | 1 startbit |
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80 | 2 car id bit 1 |
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81 | 3 car id bit 2 |
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82 | 4 car id bit 3 |
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83 | 5 track change status bit 1 |
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84 | 6 track change status bit 2 |
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85 | 7 track change status bit 3 |
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86 | 8 track change status bit 4 |
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87 | 9 sender id bit 1 |
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88 | 10 sender id bit 2 |
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89 | 11 sender id bit 3 |
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90 | 12 sender id bit 4 |
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91 | 13 device type bit 1 |
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92 | 14 device type bit 2 |
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93 | 15 device type bit 3 |
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94 | 16 stopbit |
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95 | */ |
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96 | uint16_t data; |
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97 | // produce packet |
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98 | data = ((car & 0b111) << 1) | ((status & 0b1111) << 4) | ((self_id & 0b1111) << 8) | (TRACKSWITCH_TYPE << 12); |
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99 | data |= 0b100000000000001; // make sure start/stop bits are set |
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100 | |
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101 | uint8_t index = 16; // bit count maximum |
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102 | uint8_t enable = DDR(RESPONSE_PORT) | _BV(RESPONSE_PIN); |
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103 | uint8_t disable = DDR(RESPONSE_PORT) & ~_BV(RESPONSE_PIN); |
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104 | while (index != 0) { |
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105 | if ((data & 1) != 0) { |
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106 | DDR(RESPONSE_PORT) = enable; // enable response output |
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107 | } else { |
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108 | DDR(RESPONSE_PORT) = disable; // disable response output |
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109 | } |
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110 | data = data >> 1; // next bit prepare |
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111 | index--; // decrement index |
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112 | _delay_us(49); // bit valid phase |
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113 | } |
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114 | // finally be sure to release the bus! |
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115 | DDR(RESPONSE_PORT) = disable; // disable response output |
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116 | } |
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117 | |
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118 | |
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119 | ISR ( INT0_vect ) { |
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120 | GICR &= ~_BV(INT0) ; // Disable INT0 |
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121 | // Startsignal erkannt, ab hier den Timer2 starten, |
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122 | // der liest dann alle 50µs den Zustand ein und schreibt das |
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123 | // empfangene Bit in den Puffer |
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124 | bitbuf = 0; // init |
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125 | bitbuf_len = 0b10000000; // init 1 pulse received |
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126 | TCNT2 = 0; |
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127 | TIMSK |= _BV(OCIE2); //enable timer2 interrupt |
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128 | } |
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129 | |
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130 | ISR ( TIMER2_COMP_vect ) { |
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131 | uint8_t clock; |
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132 | uint8_t state; |
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133 | uint8_t state2; |
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134 | if ((bitbuf_len & 0b10000000) == 0) clock = 0; else clock = 0xff; |
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135 | if ((bitbuf_len & 0b01000000) == 0) state = 0; else state = 0xff; |
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136 | if ((PIN(PULSE_PORT) & _BV(PULSE_BIT)) == 0) state2 = 0xff; else state2 = 0; |
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137 | |
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138 | if (clock) { |
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139 | bitbuf_len &= ~_BV(7); // switch clock to low |
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140 | // second pulse of bit |
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141 | if ((state==state2) & state2) { |
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142 | // two cycles high: packet end received |
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143 | data_len = (bitbuf_len & 0b00111111); |
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144 | TIMSK &= ~_BV(OCIE2); //disable timer2 interrupt |
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145 | GICR |= _BV(INT0) ; // Enable INT0 |
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146 | |
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147 | //data = bitbuf; // output data |
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148 | // write data of controllers to array |
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149 | if (data_len == 10) { // controller data packet |
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150 | clock = (bitbuf >> 6) & 0b00000111; |
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151 | slot[clock].speed = (bitbuf >> 1) & 0x0F; |
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152 | slot[clock].trackswitch = (bitbuf >> 5) & 1; |
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153 | // current response for this car? |
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154 | if (response != 0) { |
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155 | if ( response_car == clock) { |
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156 | // add our ID to response: |
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157 | send_response(clock, response); |
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158 | response = 0; |
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159 | } |
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160 | } |
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161 | } |
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162 | |
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163 | |
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164 | } else { |
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165 | bitbuf_len++; // increment bit counter |
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166 | bitbuf = bitbuf << 1; // shift bits |
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167 | if (state2 == 0) bitbuf |= 1; // receive logic one |
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168 | } |
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169 | } else { |
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170 | bitbuf_len |= _BV(7); // switch clock to high |
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171 | // first pulse of bit |
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172 | if (state2) { |
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173 | bitbuf_len |= _BV(6); // store new state |
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174 | } else { |
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175 | bitbuf_len &= ~_BV(6); // store new state |
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176 | } |
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177 | } |
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178 | } |
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179 | |
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180 | |
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181 | ISR (TIMER1_OVF_vect) { |
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182 | // reset car counters to overflow |
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183 | uint8_t i; |
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184 | for (i=0;i<MAX_SENSORS;i++) |
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185 | sens[i].old = 0xffff; |
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186 | } |
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187 | |
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188 | void detect_car(uint8_t idx) { |
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189 | uint16_t tmp = 0; |
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190 | sens[idx].new = TCNT1; // get current counter |
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191 | if (sens[idx].old < sens[idx].new) { |
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192 | // calculate difference |
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193 | if (sens[idx].car == 0) tmp = sens[idx].new-sens[idx].old; |
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194 | if ( (tmp > 54) && (tmp < 74) ) tmp = 1; |
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195 | else if ( (tmp > 118) && (tmp < 138) ) tmp = 2; |
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196 | else if ( (tmp > 186) && (tmp < 206) ) tmp = 3; |
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197 | else if ( (tmp > 246) && (tmp < 266) ) tmp = 4; |
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198 | else if ( (tmp > 310) && (tmp < 330) ) tmp = 5; |
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199 | else if ( (tmp > 374) && (tmp < 394) ) tmp = 6; |
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200 | else tmp = 0; |
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201 | sens[idx].car = tmp; |
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202 | } |
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203 | sens[idx].old = sens[idx].new; |
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204 | } |
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205 | |
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206 | ISR (INT1_vect) { |
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207 | // car0 detector |
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208 | detect_car(0); |
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209 | } |
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210 | |
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211 | #ifdef ANALOG_COMPARATOR |
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212 | ISR (ANA_COMP_vect) { |
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213 | // car1 detector |
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214 | detect_car(1); |
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215 | } |
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216 | #else |
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217 | // ALTERNATIV: |
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218 | ISR (TIMER1_CAPT_vect) { |
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219 | // car1 detector |
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220 | detect_car(1); |
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221 | } |
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222 | #endif |
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223 | |
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224 | |
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225 | int main(void) |
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226 | { |
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227 | uint8_t tmp; |
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228 | |
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229 | // setup data bit timer2 |
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230 | TCCR2 = (1<<CS21) | (1<<WGM21); //divide by 8, set compare match |
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231 | OCR2 = TIMER2_50US; |
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232 | |
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233 | // initialize timer1 for IR signal detection |
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234 | #ifdef ANALOG_COMPARATOR |
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235 | TCCR1B = _BV(CS01) ; // 1mhz clock |
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236 | TIMSK = _BV(OCIE2) | _BV(TOIE1) ; //enable timer1+2 |
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237 | #else |
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238 | TCCR1B = _BV(CS01) | _BV(ICNC1) | _BV(ICES1); // 1mhz clock, enable ICP on rising edge |
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239 | TIMSK = _BV(OCIE2) | _BV(TOIE1) | _BV(TICIE1); //enable timer1+2 / ICP1 |
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240 | #endif |
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241 | |
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242 | // enable both external interrupts |
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243 | // int 0 = data RX |
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244 | // int 1 = car0 input |
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245 | MCUCR = _BV(ISC00) | _BV(ISC01) | _BV(ISC10) | _BV(ISC11); // INT0/1 rising edge |
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246 | GICR = _BV(INT0) | _BV(INT1) ; // Enable INT0 + INT1 |
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247 | |
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248 | #ifdef ANALOG_COMPARATOR |
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249 | ACSR = _BV(ACIE) | _BV(ACIS1) | _BV(ACIS0); // setup analog comparator |
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250 | #endif |
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251 | |
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252 | // oscillator calibration |
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253 | // atmega8@1mhz = 0xac |
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254 | // @4mhz = ca 0xa0 |
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255 | //OSCCAL = 0xa0; |
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256 | //OSCCAL = 0x9A; |
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257 | //OSCCAL = 0xa0; // internal oscillator @ 4 mhz.... doesnt work accurate! |
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258 | |
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259 | RS232_init(); // initialize RS232 interface |
72 | 260 | RS232_puts_p(PSTR("Freeslot TrackSwitch / Pitlane v1.4\n")); |
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261 | sei(); |
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262 | |
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263 | |
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264 | DDR(SOLENOID_A_PORT) |= _BV(SOLENOID_A_PIN); |
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265 | DDR(SOLENOID_B_PORT) |= _BV(SOLENOID_B_PIN); |
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266 | |
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267 | DDR(RESPONSE_PORT) &= ~_BV(RESPONSE_PIN); // switch response off |
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268 | RESPONSE_PORT &= ~_BV(RESPONSE_PIN); // switch response off |
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269 | |
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270 | // setup pitlane output |
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271 | DDR(PIT_PORT) |= _BV(PIT_CONNECT_PIN) | _BV(PIT_GROUND_PIN); |
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272 | |
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273 | // setup LED |
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274 | DDR(LED_PORT) |= _BV(LED_PIN); |
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275 | LED_PORT |= _BV(LED_PIN); // switch LED off |
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276 | |
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277 | // CONNECT PITLANE TO MAIN TRACK |
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278 | PIT_PORT &= ~_BV(PIT_CONNECT_PIN); |
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279 | PIT_PORT |= _BV(PIT_GROUND_PIN); |
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280 | |
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281 | while (1) { |
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282 | // main loop |
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283 | |
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284 | /* |
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285 | 1 = AA |
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286 | 2 = AB |
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287 | 3 = BB |
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288 | 4 = BA |
67 | 289 | 5 = BC |
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290 | 6 = ZZ -> pitlane exit |
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291 | */ |
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292 | if (sens[0].car != sens[0].state) { |
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293 | sens[0].state = sens[0].car; |
72 | 294 | #if (TRACKSWITCH_TYPE != TYPE_PITLANE) |
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295 | if ( (sens[0].state != 0) && (slot[sens[0].state-1].trackswitch == 0) && (slot[sens[0].state-1].speed>0) ) { |
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296 | response = 2; |
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297 | response_car = sens[0].state - 1; |
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298 | |
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299 | // set inside status |
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300 | slot[sens[0].state].inside = 1; |
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301 | |
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302 | // trigger solenoid A |
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303 | RS232_putc('A'); |
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304 | RS232_putc('B'); |
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305 | RS232_putc('0'+sens[0].state); |
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306 | RS232_putc('\n'); |
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307 | |
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308 | SOLENOID_A_PORT |= _BV(SOLENOID_A_PIN); |
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309 | solenoid_delay(); |
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310 | SOLENOID_A_PORT &= ~_BV(SOLENOID_A_PIN); |
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311 | solenoid_delay(); |
72 | 312 | } else |
67 | 313 | #endif |
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314 | if (sens[0].state != 0) { |
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315 | response = 1; |
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316 | response_car = sens[0].state - 1; |
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317 | RS232_putc('A'); |
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318 | RS232_putc('A'); |
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319 | RS232_putc('0'+sens[0].state); |
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320 | RS232_putc('\n'); |
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321 | } |
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322 | } sens[0].car = 0; |
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323 | |
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324 | |
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325 | if (sens[1].car != sens[1].state) { |
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326 | sens[1].state = sens[1].car; |
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327 | if ( (sens[1].state != 0) && (slot[sens[1].state-1].trackswitch == 0) && (slot[sens[1].state-1].speed>0) ) { |
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328 | response = 5; |
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329 | response_car = sens[1].state - 1; |
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330 | |
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331 | // set inside status |
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332 | slot[sens[1].state-1].inside = 1; |
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333 | |
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334 | // trigger solenoid B |
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335 | RS232_putc('B'); |
67 | 336 | RS232_putc('C'); |
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337 | RS232_putc('0'+sens[1].state); |
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338 | RS232_putc('\n'); |
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339 | |
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340 | SOLENOID_B_PORT |= _BV(SOLENOID_B_PIN); |
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341 | solenoid_delay(); |
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342 | SOLENOID_B_PORT &= ~_BV(SOLENOID_B_PIN); |
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343 | solenoid_delay(); |
72 | 344 | } else |
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345 | if (sens[1].state != 0) { |
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346 | response = 3; |
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347 | response_car = sens[1].state - 1; |
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348 | RS232_putc('B'); |
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349 | RS232_putc('B'); |
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350 | RS232_putc('0'+sens[1].state); |
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351 | RS232_putc('\n'); |
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352 | } |
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353 | } sens[1].car = 0; |
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354 | |
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355 | // TODO: At the moment, all "inside" cars gets exit response, but probably only the last response will be sent |
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356 | // we have to detect which car is passing sensor2 - but at the moment we are lack of external interrupt source |
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357 | if ( (PIN(SENS2_PORT) & _BV(SENS2_PIN)) != 0 ) { |
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358 | // set inside status |
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359 | for (tmp=0; tmp<MAX_SLOTS; tmp++) |
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360 | if (slot[tmp].inside) { |
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361 | slot[tmp].inside = 0; |
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362 | } |
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363 | response = 6; |
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364 | response_car = 0; |
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365 | RS232_puts_p(PSTR("PIT:EXIT\n")); |
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366 | } |
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367 | |
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368 | if (sens[2].car != sens[2].state) { |
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369 | sens[2].state = sens[2].car; |
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370 | if (sens[2].state != 0) { |
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371 | response = 6; |
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372 | response_car = sens[2].state-1; |
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373 | |
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374 | // set inside status |
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375 | slot[sens[2].state-1].inside = 0; |
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376 | |
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377 | RS232_putc('Z'); |
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378 | RS232_putc('Z'); |
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379 | RS232_putc('0'+sens[2].state); |
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380 | RS232_putc('\n'); |
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381 | } |
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382 | } sens[2].car = 0; |
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383 | |
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384 | // enable LED when car is in pitlane |
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385 | LED_PORT |= _BV(LED_PIN); |
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386 | for (tmp=0; tmp<MAX_SLOTS; tmp++) |
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387 | if (slot[tmp].inside) LED_PORT &= ~_BV(LED_PIN); |
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388 | |
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389 | |
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390 | } // main loop end |
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391 | }; |
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392 |