sanguino/cores/arduino/WInterrupts.c

Fri, 17 Nov 2017 10:13:31 +0100

author
mdd
date
Fri, 17 Nov 2017 10:13:31 +0100
changeset 3
770b218a4931
parent 2
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permissions
-rw-r--r--

proper configuration, homing and planner optimization

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1 /* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */
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2
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3 /*
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4 Part of the Wiring project - http://wiring.uniandes.edu.co
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5
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6 Copyright (c) 2004-05 Hernando Barragan
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7
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8 This library is free software; you can redistribute it and/or
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9 modify it under the terms of the GNU Lesser General Public
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10 License as published by the Free Software Foundation; either
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11 version 2.1 of the License, or (at your option) any later version.
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12
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13 This library is distributed in the hope that it will be useful,
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14 but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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16 Lesser General Public License for more details.
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17
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18 You should have received a copy of the GNU Lesser General
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19 Public License along with this library; if not, write to the
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20 Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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21 Boston, MA 02111-1307 USA
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22
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23 Modified 24 November 2006 by David A. Mellis
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24 Modified 1 August 2010 by Mark Sproul
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25 */
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26
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27 #include <inttypes.h>
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28 #include <avr/io.h>
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29 #include <avr/interrupt.h>
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30 #include <avr/pgmspace.h>
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31 #include <stdio.h>
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32
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33 #include "wiring_private.h"
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34
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35 static volatile voidFuncPtr intFunc[EXTERNAL_NUM_INTERRUPTS];
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36 // volatile static voidFuncPtr twiIntFunc;
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37
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38 void attachInterrupt(uint8_t interruptNum, void (*userFunc)(void), int mode) {
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39 if(interruptNum < EXTERNAL_NUM_INTERRUPTS) {
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40 intFunc[interruptNum] = userFunc;
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41
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42 // Configure the interrupt mode (trigger on low input, any change, rising
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43 // edge, or falling edge). The mode constants were chosen to correspond
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44 // to the configuration bits in the hardware register, so we simply shift
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45 // the mode into place.
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46
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47 // Enable the interrupt.
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48
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49 switch (interruptNum) {
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50 #if defined(__AVR_ATmega32U4__)
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51 // I hate doing this, but the register assignment differs between the 1280/2560
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52 // and the 32U4. Since avrlib defines registers PCMSK1 and PCMSK2 that aren't
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53 // even present on the 32U4 this is the only way to distinguish between them.
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54 case 0:
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55 EICRA = (EICRA & ~((1<<ISC00) | (1<<ISC01))) | (mode << ISC00);
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56 EIMSK |= (1<<INT0);
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57 break;
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58 case 1:
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59 EICRA = (EICRA & ~((1<<ISC10) | (1<<ISC11))) | (mode << ISC10);
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60 EIMSK |= (1<<INT1);
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61 break;
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62 #elif defined(EICRA) && defined(EICRB) && defined(EIMSK)
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63 case 2:
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64 EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
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65 EIMSK |= (1 << INT0);
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66 break;
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67 case 3:
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68 EICRA = (EICRA & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
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69 EIMSK |= (1 << INT1);
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70 break;
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71 case 4:
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72 EICRA = (EICRA & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
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73 EIMSK |= (1 << INT2);
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74 break;
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75 case 5:
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76 EICRA = (EICRA & ~((1 << ISC30) | (1 << ISC31))) | (mode << ISC30);
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77 EIMSK |= (1 << INT3);
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78 break;
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79 case 0:
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80 EICRB = (EICRB & ~((1 << ISC40) | (1 << ISC41))) | (mode << ISC40);
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81 EIMSK |= (1 << INT4);
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82 break;
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83 case 1:
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84 EICRB = (EICRB & ~((1 << ISC50) | (1 << ISC51))) | (mode << ISC50);
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85 EIMSK |= (1 << INT5);
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86 break;
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87 case 6:
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88 EICRB = (EICRB & ~((1 << ISC60) | (1 << ISC61))) | (mode << ISC60);
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89 EIMSK |= (1 << INT6);
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90 break;
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91 case 7:
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92 EICRB = (EICRB & ~((1 << ISC70) | (1 << ISC71))) | (mode << ISC70);
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93 EIMSK |= (1 << INT7);
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94 break;
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95 #else
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96 case 0:
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97 #if defined(EICRA) && defined(ISC00) && defined(EIMSK)
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98 EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
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99 EIMSK |= (1 << INT0);
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100 #elif defined(MCUCR) && defined(ISC00) && defined(GICR)
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101 MCUCR = (MCUCR & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
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102 GICR |= (1 << INT0);
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103 #elif defined(MCUCR) && defined(ISC00) && defined(GIMSK)
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104 MCUCR = (MCUCR & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
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105 GIMSK |= (1 << INT0);
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106 #else
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107 #error attachInterrupt not finished for this CPU (case 0)
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108 #endif
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109 break;
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110
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111 case 1:
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112 #if defined(EICRA) && defined(ISC10) && defined(ISC11) && defined(EIMSK)
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113 EICRA = (EICRA & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
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114 EIMSK |= (1 << INT1);
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115 #elif defined(MCUCR) && defined(ISC10) && defined(ISC11) && defined(GICR)
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116 MCUCR = (MCUCR & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
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117 GICR |= (1 << INT1);
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118 #elif defined(MCUCR) && defined(ISC10) && defined(GIMSK) && defined(GIMSK)
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119 MCUCR = (MCUCR & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
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120 GIMSK |= (1 << INT1);
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121 #else
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122 #warning attachInterrupt may need some more work for this cpu (case 1)
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123 #endif
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124 break;
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125
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126 case 2:
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127 #if defined(EICRA) && defined(ISC20) && defined(ISC21) && defined(EIMSK)
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128 EICRA = (EICRA & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
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129 EIMSK |= (1 << INT2);
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130 #elif defined(MCUCR) && defined(ISC20) && defined(ISC21) && defined(GICR)
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131 MCUCR = (MCUCR & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
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132 GICR |= (1 << INT2);
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133 #elif defined(MCUCR) && defined(ISC20) && defined(GIMSK) && defined(GIMSK)
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134 MCUCR = (MCUCR & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
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135 GIMSK |= (1 << INT2);
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136 #endif
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137 break;
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138 #endif
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139 }
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140 }
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141 }
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142
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143 void detachInterrupt(uint8_t interruptNum) {
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144 if(interruptNum < EXTERNAL_NUM_INTERRUPTS) {
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145 // Disable the interrupt. (We can't assume that interruptNum is equal
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146 // to the number of the EIMSK bit to clear, as this isn't true on the
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147 // ATmega8. There, INT0 is 6 and INT1 is 7.)
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148 switch (interruptNum) {
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149 #if defined(__AVR_ATmega32U4__)
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150 case 0:
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151 EIMSK &= ~(1<<INT0);
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152 break;
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153 case 1:
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154 EIMSK &= ~(1<<INT1);
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155 break;
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156 #elif defined(EICRA) && defined(EICRB) && defined(EIMSK)
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157 case 2:
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158 EIMSK &= ~(1 << INT0);
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159 break;
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160 case 3:
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161 EIMSK &= ~(1 << INT1);
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162 break;
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163 case 4:
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164 EIMSK &= ~(1 << INT2);
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165 break;
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166 case 5:
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167 EIMSK &= ~(1 << INT3);
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168 break;
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169 case 0:
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170 EIMSK &= ~(1 << INT4);
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171 break;
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172 case 1:
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173 EIMSK &= ~(1 << INT5);
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174 break;
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175 case 6:
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176 EIMSK &= ~(1 << INT6);
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177 break;
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178 case 7:
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179 EIMSK &= ~(1 << INT7);
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180 break;
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181 #else
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182 case 0:
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183 #if defined(EIMSK) && defined(INT0)
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184 EIMSK &= ~(1 << INT0);
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185 #elif defined(GICR) && defined(ISC00)
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186 GICR &= ~(1 << INT0); // atmega32
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187 #elif defined(GIMSK) && defined(INT0)
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188 GIMSK &= ~(1 << INT0);
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189 #else
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190 #error detachInterrupt not finished for this cpu
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191 #endif
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192 break;
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193
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194 case 1:
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195 #if defined(EIMSK) && defined(INT1)
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196 EIMSK &= ~(1 << INT1);
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197 #elif defined(GICR) && defined(INT1)
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198 GICR &= ~(1 << INT1); // atmega32
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199 #elif defined(GIMSK) && defined(INT1)
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200 GIMSK &= ~(1 << INT1);
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201 #else
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202 #warning detachInterrupt may need some more work for this cpu (case 1)
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203 #endif
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204 break;
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205 #endif
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206 }
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207
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208 intFunc[interruptNum] = 0;
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209 }
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210 }
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211
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212 /*
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213 void attachInterruptTwi(void (*userFunc)(void) ) {
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214 twiIntFunc = userFunc;
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215 }
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216 */
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217
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218 #if defined(__AVR_ATmega32U4__)
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219 SIGNAL(INT0_vect) {
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220 if(intFunc[EXTERNAL_INT_0])
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221 intFunc[EXTERNAL_INT_0]();
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222 }
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223
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224 SIGNAL(INT1_vect) {
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225 if(intFunc[EXTERNAL_INT_1])
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226 intFunc[EXTERNAL_INT_1]();
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227 }
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228
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229 #elif defined(EICRA) && defined(EICRB)
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230
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231 SIGNAL(INT0_vect) {
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232 if(intFunc[EXTERNAL_INT_2])
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233 intFunc[EXTERNAL_INT_2]();
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234 }
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235
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236 SIGNAL(INT1_vect) {
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237 if(intFunc[EXTERNAL_INT_3])
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238 intFunc[EXTERNAL_INT_3]();
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239 }
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240
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241 SIGNAL(INT2_vect) {
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242 if(intFunc[EXTERNAL_INT_4])
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243 intFunc[EXTERNAL_INT_4]();
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244 }
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245
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246 SIGNAL(INT3_vect) {
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247 if(intFunc[EXTERNAL_INT_5])
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248 intFunc[EXTERNAL_INT_5]();
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249 }
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250
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251 SIGNAL(INT4_vect) {
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252 if(intFunc[EXTERNAL_INT_0])
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253 intFunc[EXTERNAL_INT_0]();
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254 }
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255
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256 SIGNAL(INT5_vect) {
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257 if(intFunc[EXTERNAL_INT_1])
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258 intFunc[EXTERNAL_INT_1]();
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259 }
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260
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261 SIGNAL(INT6_vect) {
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262 if(intFunc[EXTERNAL_INT_6])
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263 intFunc[EXTERNAL_INT_6]();
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264 }
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265
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266 SIGNAL(INT7_vect) {
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267 if(intFunc[EXTERNAL_INT_7])
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268 intFunc[EXTERNAL_INT_7]();
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269 }
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270
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271 #else
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272
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273 SIGNAL(INT0_vect) {
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274 if(intFunc[EXTERNAL_INT_0])
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275 intFunc[EXTERNAL_INT_0]();
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276 }
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277
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278 SIGNAL(INT1_vect) {
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279 if(intFunc[EXTERNAL_INT_1])
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280 intFunc[EXTERNAL_INT_1]();
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281 }
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282
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283 #if defined(EICRA) && defined(ISC20)
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284 SIGNAL(INT2_vect) {
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285 if(intFunc[EXTERNAL_INT_2])
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286 intFunc[EXTERNAL_INT_2]();
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287 }
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288 #endif
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289
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290 #endif
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291
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292 /*
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293 SIGNAL(SIG_2WIRE_SERIAL) {
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294 if(twiIntFunc)
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295 twiIntFunc();
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296 }
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297 */
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298

mercurial